F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

Download PDF
ID 683281
Date 12/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example 1.8. Transceiver Toolkit
2. Design Example Description x
2.1. Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL
1. Quick Start Guide
2. Design Example Description
3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

2.3. Simulation Design Example

The F-Tile CPRI PHY Intel® FPGA IP design example generates a simulation testbench and simulation files that instantiate the F-Tile CPRI PHY Intel® FPGA IP core when you select the Simulation option.
Figure 4. Block Diagram for 10.1316, 12.1651, and 24.33024 Gbps (with and without RS-FEC) Line Rates
Figure 5. Block Diagram for 1.228, 2.4576, 3.072, 4.9152, 6.144, and 9.8304 Gbps Line Rate

In this design example, the simulation testbench provides basic functionality such as startup and wait for lock, transmit, and receive packets.

The successful test run displays output confirming the following behavior:
  1. The client logic resets the IP core.
  2. The client logic waits for the RX datapath alignment.
  3. The client logic transmits hyperframes on the TX MII interface and waits for five hyperframes to be received on the RX MII interface. Hyperframes are transmitted and received on the MII interfaces, per the CPRI v7.0 specifications.
    Note: The CPRI designs that target 1.2, 2.4, 3, 4.9, 6.1, and 9.8 Gbps line rates use 8b/10b interface and the designs that target 10.1, 12.1, and 24.3 Gbps (with and without RS-FEC) use MII interface.
    Note: This design example includes a round trip counter to count the round trip latency from TX to RX.
  4. The client logic reads the round trip latency value and checks for the content and correctness of the hyperframes data on the RX MII side once the counter completes the round trip latency count.
Related Information
Level Two Title