F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

ID 683281
Date 12/13/2021

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1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 21.4
IP Version 3.1.0

The F-Tile CPRI PHY Intel® FPGA IP core provides a simulation testbench and hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.

Intel® also provides a compilation-only example project that you can use to quickly estimate IP core area and timing.

The F-Tile CPRI PHY Intel® FPGA IP core allows you to generate design examples for all supported combinations of CPRI channels and CPRI line bit rates. The testbench and design example support multiple parameter combinations of the F-Tile CPRI PHY Intel® FPGA IP core.

Figure 1. Development Steps for the Design Example