1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example 1.8. Transceiver Toolkit
2.4. Hardware Design Example
Figure 6. Hardware Design Example Block Diagram
The F-Tile CPRI PHY Intel® FPGA IP core hardware design example includes the following components:
- F-Tile CPRI PHY Intel® FPGA IP core.
- Packet client logic block that generates and receives traffic.
- Round trip counter.
- IOPLL to generate the sampling clock for deterministic latency logic inside the IP, and the round trip counter component at testbench.
- System PLL to generate the system clocks for the IP.
- Avalon® memory-mapped address decoder to decode reconfiguration address space for CPRI PHY Reconfiguration Interface, PMA Avalon® Memory-Mapped Interface, and Datapath Avalon® Memory-Mapped Interface.
- Sources and probes for asserting resets and monitoring the clocks and a few status bits.
- JTAG controller that communicates with the System Console. You communicate with the client logic through System Console.