F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

ID 683281
Date 12/13/2021

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2.2.6. IOPLL

The IOPLL Intel FPGA IP generates a 250 MHz clock from a 100 MHz reference clock. The 250 MHz clock is the sampling clock (sampling_clk) for the deterministic latency measurement. For more information, refer to IOPLL Intel FPGA IP Core.