F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

ID 683281
Date 12/13/2021
Public

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2.6. Design Example Registers

Table 23.  Design Example Registers
Channel Number Base Address

(Byte Address)

Register Type
0 0x00000000 CPRI PHY reconfiguration interface registers for Channel 0
0x00100000 Datapath Avalon® memory-mapped interface registers for Channel 0
0x00200000 PMA Avalon® memory-mapped interface registers for Channel 0
1 2 0x01000000 CPRI PHY reconfiguration interface registers for Channel 1
0x01100000 Datapath Avalon® memory-mapped interface registers for Channel 1
0x01200000 PMA Avalon® memory-mapped interface registers for Channel 1
22 0x02000000 CPRI PHY reconfiguration registers for Channel 2
0x02100000 Datapath Avalon® memory-mapped interface registers for Channel 2
0x02200000 PMA Avalon® memory-mapped interface registers for Channel 2
32 0x03000000 CPRI PHY reconfiguration interface registers for Channel 3
0x03100000 Datapath Avalon® memory-mapped interface registers for Channel 3
0x03200000 PMA Avalon® memory-mapped interface registers for Channel 3
2 These registers are reserved if the channel is not used.