Battery Management System Reference Design

ID 683279
Date 4/02/2016
Document Table of Contents BMS Reference Design DEKF IP (Design C)

The DEKF IP includes all calculations in the DEKF.

The Nios II processor only communicates with the host, sends inputs, and receives results. The reference design includes the model file Ekf_Core.slx. A DSP Builder-generated direct implementation of the algorithm in the FPGA fabric executes quickly but uses too many FPGA resources for a low-cost FPGA device. However, the DSP Builder ALU folding automatically generates a design which reuses FPGA logic.The ALU folder saves around 90% of the FPGA resources in this design.