Battery Management System Reference Design

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ID 683279
Date 4/02/2016
Public
Document Table of Contents
Document Table of Contents x
1. Battery Management System Reference Design
1. Battery Management System Reference Design x
1.1. BMS Reference Design Features 1.2. BMS Reference Design Getting Started 1.3. BMS Reference Design Functional Description 1.4. BMS Reference Design FPGA Resource Usage 1.5. BMS Reference Design Benchmarking 1.6. Acknowledgements for the BMS Reference Design
1.2. BMS Reference Design Getting Started x
1.2.1. BMS Reference Design Software Requirements 1.2.2. BMS Reference Design Hardware Requirements 1.2.3. Downloading and Installing the BMS Reference Design 1.2.4. Setting Up the MAX 10 Development Board 1.2.5. Compiling the FPGA Hardware Design for the BMS Reference Design 1.2.6. Compiling the Nios Software for the BMS Reference Design 1.2.7. Programming the BMS Reference Design Hardware onto the Device 1.2.8. Downloading the BMS Reference Design Nios II Software to the Device 1.2.9. MATLAB Simulink Top-Level Design for the BMS Reference Design 1.2.10. Running the BMS Reference Design in a System-in-the-Loop Simulation
1.3. BMS Reference Design Functional Description x
1.3.1. BMS Reference Design Car Model 1.3.2. BMS Reference Design Battery Model 1.3.3. BMS Reference Design DEKF Technique 1.3.4. BMS Reference Design Hardware Implementation
1.3.4. BMS Reference Design Hardware Implementation x
1.3.4.1. BMS Reference Design Matrix Processor 1.3.4.2. BMS Reference Design uCode Controller Interface 1.3.4.3. BMS Reference Design DEKF IP (Design C)
1. Battery Management System Reference Design

1.3.4.3. BMS Reference Design DEKF IP (Design C)

The DEKF IP includes all calculations in the DEKF.

The Nios II processor only communicates with the host, sends inputs, and receives results. The reference design includes the model file Ekf_Core.slx. A DSP Builder-generated direct implementation of the algorithm in the FPGA fabric executes quickly but uses too many FPGA resources for a low-cost FPGA device. However, the DSP Builder ALU folding automatically generates a design which reuses FPGA logic.The ALU folder saves around 90% of the FPGA resources in this design.

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