1.3.4. BMS Reference Design Hardware Implementation
The reference design includes three different designs to implement the DEKF algorithm:
- Design A,which has a Nios II processor with floating-point acceleration
- Design B, which has a Nios II processor with floating-point acceleration and floating-point matrix processor
- Design C, which has a Nios II processor and DEKF algorithm implemented in dedicated floating-point IP
The reference design creates the dedicated floating-point IP using Altera’s DSP Builder advanced blockset. In each design, every functional component takes charge of different tasks, including system-in-the-loop communication with MATLAB Simulink, cell link list management, DEKF calculation. In the three designs, the Nios processor II controls the system-in-the-loop and cell link tasks. In design B, both the Nios II processor and matrix processor perform the DEKF calculation, and the matrix processor processes most of the matrix calculations. Finally, in design C, DSP Builder IP processes all DEKF calculations.
To switch between different implementation methods, modify this line in source file
\software \bms_soc_microc \soc_kalman.h: // 0 - Nios2 only // 1 - Matrix processor // 2 - DSP Builder IP #define ACC 1
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