Battery Management System Reference Design

ID 683279
Date 4/02/2016
Document Table of Contents BMS Reference Design Matrix Processor

The matrix processor is a generic matrix processor that Altera developed using the DSP Builder advanced blockset. It can perform sequences of different matrix operations.

You can select the maximum size of matrices to use to scale the usage of internal memory to fit the desired application. The matrix processor includes two data processing cores: Faddeev and matrix multiply cores. The Faddeev core can calculate the operation: D + C * A -1 * B. The matrix multiply core can calculate the (A * B) and (A * B + C) matrix expressions.

Figure 22. Matrix Processor Block Diagram

The matrix processor interface is the main interface between the matrix processor and the external environment. It programs the matrix processor for certain uCode, provides input matrix argumentss and reads-back results.