Quartus® Prime Pro Edition User Guide: Block-Based Design
2.2.2.1. Clocks in Safety Designs
Agilex 5 devices implement global routing using a programmable clock routing network. This architecture divides the device into evenly sized clock sectors. You can route a global signal from any clock source in the device, to a clock tree covering any arbitrary rectangular array of these clock sectors. The total insertion delay for the clock network depends on the number of clock resources needed to implement the clock tree, increasing with the distance of the furthest clock destination from the signal source. For more information about the Agilex 5 clock architecture, refer to the Clocking and PLL User Guide: Agilex 5 FPGAs and SoCs.
This safety flow supports enhanced preservation of global signal routing to safety partitions. Preserving the topology of the global signal routing can help minimize variation in timing results. Clock routing delay has a relatively small impact on clock transfers within a single clock domain (only typically affecting clock uncertainty calculations), but the impact can be more significant if there are synchronous clock-to-clock transfers in the design.
The downside to preserving global signal routing is that it can complicate design integration if safety partitions with preserved clocks are combined from different design creation flow sources. If you do not carefully plan the floorplan of these preserved clock sources, conflicts in routing usage can lead to Fitter errors.
Clock Preservation Design Considerations
Single Safety Partition
Clock preservation is straightforward if your design uses only one safety partition. If the clock source is inside the partition, the Quartus® Prime Pro Edition software automatically preserves all clock routing. If the clock source is outside the partition, the Quartus® Prime software only preserves the clock tree routing when you apply a Preserve Clock assignment to the signal.
If the clock source remains unchanged and placed in the same location as the design creation flow, the Quartus® Prime software also preserves the routing from clock source to clock tree. If you change the clock source or clock source location, the Quartus® Prime software reimplements this routing, with possibly a different delay. Altera recommends maintaining the same clock source location when Preserve clock is Enabled.
By default, the Quartus® Prime compiler expands the clock region of any clock signal driving a safety partition to drive the entire device. If preserved, the clock signal is available throughout the device for any nonsafety logic. You can specify a smaller region by adding a Clock Region assignment on the signal. Ensure the size is appropriate for future usage of the the signal in nonsafety logic.
Multiple Safety Partitions
With multiple safety partitions, consider clock preservation more carefully. If all safety partitions are included in the same design creation flow, with consistent clock sources, clock preservation works reliably for all signals. If you create the partitions using different design creation compilations, ensure any preserved clock routes do not use the same programmable clock routing resources. You should specify Clock Region assignments so that the clock sectors targeted do not overlap. If the clock trees must overlap, specify Clock Region assignments in the Assignment Editor to ensure the clock trees do not use the same clock routing resources within a sector. To minimize risk of clock routing conflicts, ensure the clock spines targeted by these assignments vary by 2 or more. Do not use clock spine values of 2 and 3 for two global signals that share sectors. Values of 2 and 4 are better, 2 and 5 are best.
If two safety partitions from different design creation compilations share the same clock source in a design modification compilation, you cannot preserve the global signal from both design creation compiles. Apply a Preserve Clock assignment to at most one of the original clock signals, and ensure the clock region of that signal covers all expected safety partition Logic Lock regions in the corresponding design creation compilation.
Clock source (pin, PLL, promoted fabric signal) is outside the safety logic
If the clock enters the safety region:
- Preserve the clock tree over the safety and nonsafety usage by ensuring Preserve Clock assignment is Enabled for the partition or clock signal.
- Ensure you implement Clock Region assignments to account for future expansion of nonsafety logic, preferably full-device clock regions
- Do not preserve the insertion path (so it can find a PLL as it may move around). You might see some timing variation because of jitter factors from insertion path.
- Do not preserve the insertion path and lock the PLL location, otherwise the Quartus® Prime compilation fails.
If the clock is only in the nonsafety logic, proceed normally, nothing special to do.
Clock source (pin, PLL, promoted fabric signal) is inside the safety logic
- The Quartus® Prime software preserves the reference clock, PLL, entire HSIO, insertion path, and clock tree.
If the clock must go outside of safety partition for use by nonsafety logic, refer to Clock source (pin, PLL, promoted fabric signal) is outside the safety logic