Quartus® Prime Pro Edition User Guide: Block-Based Design
ID
683247
Date
8/30/2025
Public
1.1. Block-Based Design Terminology
1.2. Block-Based Design Overview
1.3. Design Methodologies Overview
1.4. Design Partitioning
1.5. Design Block Reuse Flows
1.6. Incremental Block-Based Compilation Flow
1.7. Setting-Up Team-Based Designs
1.8. Bottom-Up Design Considerations
1.9. Debugging Block-Based Designs with the Signal Tap Logic Analyzer
1.10. Block-Based Design Flows Revision History
3.1. Preserving the Device Resources
3.2. Fixing the Safety Partitions to Logic Lock Regions
3.3. Exporting and Importing Safety Logic Partitions
3.4. I/O Banks in Safety Partitions
3.5. Safety Region Verification Tool
3.6. Implementing Partitions for the Safety Separation Design Flow Revision History
3.4.1. Preserving GPIO IP and the I/Os in I/O Banks in Safety Partitions
3.4.2. Preserving IOPLL IP in I/O Banks in Safety Partitions
3.4.3. Preserving I/Os (other than GPIO IP I/Os) in I/O Banks in Safety Partitions
3.4.4. Verifying the Preserved I/Os in the Safety Partition
3.4.5. HSIO Bank 3A in a Safety Partition
1. Block-Based Design Flows
The Quartus® Prime Pro Edition software supports block-based design flows, also known as modular or hierarchical design flows.
You can designate a design block as a design partition in order to reuse the block. A design partition is a logical, named, hierarchical boundary assignment that you can apply to a design instance. Block-based design flows enable the following:
- Design block reuse—export and reuse of design blocks in other projects
You can reuse design blocks with the same periphery configuration, share a synthesized design block with another designer, or replicate placed and routed IP in another project. Design, implement, and verify core or periphery blocks once, and then reuse those blocks multiple times across different projects that use the same device.
Section Content
Block-Based Design Terminology
Block-Based Design Overview
Design Methodologies Overview
Design Partitioning
Design Block Reuse Flows
Incremental Block-Based Compilation Flow
Setting-Up Team-Based Designs
Bottom-Up Design Considerations
Debugging Block-Based Designs with the Signal Tap Logic Analyzer
Block-Based Design Flows Revision History