Quartus® Prime Pro Edition User Guide: Block-Based Design

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ID 683247
Date 8/30/2025
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Block-Based Design Flows 2. About Functional Safety Separation Design Flow 3. Implementing Partitions for the Safety Separation Design Flow 4. Quartus® Prime Pro Edition User Guide: Block-Based Design Document Archive A. Quartus® Prime Pro Edition User Guides
1. Block-Based Design Flows x
1.1. Block-Based Design Terminology 1.2. Block-Based Design Overview 1.3. Design Methodologies Overview 1.4. Design Partitioning 1.5. Design Block Reuse Flows 1.6. Incremental Block-Based Compilation Flow 1.7. Setting-Up Team-Based Designs 1.8. Bottom-Up Design Considerations 1.9. Debugging Block-Based Designs with the Signal Tap Logic Analyzer 1.10. Block-Based Design Flows Revision History
1.2. Block-Based Design Overview x
1.2.1. Design Block Reuse Overview 1.2.2. Incremental Block-Based Compilation Overview
1.2.1. Design Block Reuse Overview x
1.2.1.1. Design Block Reuse Examples
1.3. Design Methodologies Overview x
1.3.1. Top-Down Design Methodology Overview 1.3.2. Bottom-Up Design Methodology Overview 1.3.3. Team-Based Design Methodology Overview
1.4. Design Partitioning x
1.4.1. Planning Partitions for Periphery IP, Clocks, and PLLs 1.4.2. Creating Design Partitions 1.4.3. Design Partition Guidelines
1.5. Design Block Reuse Flows x
1.5.1. Reusing Core Partitions 1.5.2. Reusing Root Partitions 1.5.3. Reserved Core Entity Re-Binding 1.5.4. Viewing Quartus Database File Information
1.5.1. Reusing Core Partitions x
1.5.1.1. Step 1: Developer: Create a Design Partition 1.5.1.2. Step 2: Developer: Compile and Export the Core Partition 1.5.1.3. Step 3: Developer: Create a Black Box File 1.5.1.4. Step 4: Consumer: Add the Core Partition and Compile
1.5.2. Reusing Root Partitions x
1.5.2.1. Step 1: Developer: Create a Reserved Core Partition 1.5.2.2. Step 2: Developer: Define a Logic Lock Region 1.5.2.3. Step 3: Developer: Compile and Export the Root Partition 1.5.2.4. Step 4: Consumer: Add the Root Partition and Compile
1.5.4. Viewing Quartus Database File Information x
1.5.4.1. QDB File Attribute Types
1.6. Incremental Block-Based Compilation Flow x
1.6.1. Design Abstraction
1.6.1. Design Abstraction x
1.6.1.1. Empty Partition Clock Source Preservation
1.7. Setting-Up Team-Based Designs x
1.7.1. Creating a Top-Level Project for a Team-Based Design
1.7.1. Creating a Top-Level Project for a Team-Based Design x
1.7.1.1. Prepare a Design Partition for Project Integration
2. About Functional Safety Separation Design Flow x
2.1. Work Flows 2.2. Design Considerations 2.3. Limitations 2.4. About Functional Safety Separation Design Flow Revision History
2.1. Work Flows x
2.1.1. Design Creation Flow 2.1.2. Design Modification Flow
2.2. Design Considerations x
2.2.1. About Safety Logic Partitions and Logic Lock Regions 2.2.2. Clocks, PLLs and Resets 2.2.3. Routing Across Safety Logic Partitions
2.2.2. Clocks, PLLs and Resets x
2.2.2.1. Clocks in Safety Designs
2.2.3. Routing Across Safety Logic Partitions x
2.2.3.1. Routing to Preserve Safety Partitions
3. Implementing Partitions for the Safety Separation Design Flow x
3.1. Preserving the Device Resources 3.2. Fixing the Safety Partitions to Logic Lock Regions 3.3. Exporting and Importing Safety Logic Partitions 3.4. I/O Banks in Safety Partitions 3.5. Safety Region Verification Tool 3.6. Implementing Partitions for the Safety Separation Design Flow Revision History
3.4. I/O Banks in Safety Partitions x
3.4.1. Preserving GPIO IP and the I/Os in I/O Banks in Safety Partitions 3.4.2. Preserving IOPLL IP in I/O Banks in Safety Partitions 3.4.3. Preserving I/Os (other than GPIO IP I/Os) in I/O Banks in Safety Partitions 3.4.4. Verifying the Preserved I/Os in the Safety Partition 3.4.5. HSIO Bank 3A in a Safety Partition
Answers to Top FAQs
1. Block-Based Design Flows
2. About Functional Safety Separation Design Flow
3. Implementing Partitions for the Safety Separation Design Flow
4. Quartus® Prime Pro Edition User Guide: Block-Based Design Document Archive
A. Quartus® Prime Pro Edition User Guides

2. About Functional Safety Separation Design Flow

This design flow for the Quartus® Prime Pro Edition software for Agilex™ 5 Devices significantly reduces the certification efforts for the lifetime of an FPGA-based industrial system containing both safety critical and nonsafety critical components. This document describes how to use the design flow with a blinking LEDs design example.

Industrial machinery manufacturers throughout the world experience the continuous pressure to reduce system cost, extend performance and efficiency, and deliver to ever reduced timescales. For products in safety critical environments, designers also strive to ensure safe behavior with compliance to IEC 61508: Functional Safety of electrical/electronic/programmable electronic safety-related systems and ISO 26262: Road vehicles - Functional safety.

Functional safety designs require recertification only when you modify logic in the design, because the FPGA programming file changes. By using the functional safety separation flow in the software, you create partitions for safety logic separate from standard (nonsafety) logic. Safety critical areas of the design remain the same (at the bit level) when you modify standard areas in your design. With this flow, you can reduce the amount of required recertification

You can create safety and nonsafety regions (or partitions) on a single Agilex™ 5 device. When you only change nonsafety regions, the safety regions are fully preserved. The design flow provides the evidence that the placement and routing in the safety regions are identical to a previous hardware compilation.

For compliance with IEC61508, consider the Quartus® Prime software an offline support tool, not an online safety-related software tool. The Quartus® Prime software includes components that are considered T2 and T3 class as per IEC61508 Part4 3.2.11.

This flow extends the widely-adopted, proven Quartus® Prime incremental block-based compilation flow.

The incremental block-based compilation flow maps the design hierarchy to design partitions that the Quartus® Prime software treats separately during compilation. Altera defines a design partition as a logical partition. You use design partitions with a physical placement constraint, a Logic Lock region, to form the foundation for the safety flow.

In the functional safety separation flow, you categorize design partitions as either safety partitions, which require complete preservation, or nonsafety partitions.

When you declare a design partition, every hierarchy within that partition becomes part of the same partition. When you create new partitions for hierarchies within an existing partition, the logic within the new lower-level partition is no longer part of the higher-level partition.

Figure 18. Partitions in a Design Hierarchy B and F-G are design partitions. Design partition B includes entity B which contains sub-entities D and E. Design partition F-G includes entities F and G. The root partition, top, contains entities A and C which are not assigned to any other design partition.


Figure 19. Logic Lock Regions for Partitions in a Design Hierarchy

Use a Logic Lock region to create a physical placement constraint for the logical partition B.



Section Content
Work Flows
Design Considerations
Limitations
About Functional Safety Separation Design Flow Revision History

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