Quartus® Prime Pro Edition User Guide: Block-Based Design

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ID 683247
Date 8/30/2025
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Block-Based Design Flows 2. About Functional Safety Separation Design Flow 3. Implementing Partitions for the Safety Separation Design Flow 4. Quartus® Prime Pro Edition User Guide: Block-Based Design Document Archive A. Quartus® Prime Pro Edition User Guides
1. Block-Based Design Flows x
1.1. Block-Based Design Terminology 1.2. Block-Based Design Overview 1.3. Design Methodologies Overview 1.4. Design Partitioning 1.5. Design Block Reuse Flows 1.6. Incremental Block-Based Compilation Flow 1.7. Setting-Up Team-Based Designs 1.8. Bottom-Up Design Considerations 1.9. Debugging Block-Based Designs with the Signal Tap Logic Analyzer 1.10. Block-Based Design Flows Revision History
1.2. Block-Based Design Overview x
1.2.1. Design Block Reuse Overview 1.2.2. Incremental Block-Based Compilation Overview
1.2.1. Design Block Reuse Overview x
1.2.1.1. Design Block Reuse Examples
1.3. Design Methodologies Overview x
1.3.1. Top-Down Design Methodology Overview 1.3.2. Bottom-Up Design Methodology Overview 1.3.3. Team-Based Design Methodology Overview
1.4. Design Partitioning x
1.4.1. Planning Partitions for Periphery IP, Clocks, and PLLs 1.4.2. Creating Design Partitions 1.4.3. Design Partition Guidelines
1.5. Design Block Reuse Flows x
1.5.1. Reusing Core Partitions 1.5.2. Reusing Root Partitions 1.5.3. Reserved Core Entity Re-Binding 1.5.4. Viewing Quartus Database File Information
1.5.1. Reusing Core Partitions x
1.5.1.1. Step 1: Developer: Create a Design Partition 1.5.1.2. Step 2: Developer: Compile and Export the Core Partition 1.5.1.3. Step 3: Developer: Create a Black Box File 1.5.1.4. Step 4: Consumer: Add the Core Partition and Compile
1.5.2. Reusing Root Partitions x
1.5.2.1. Step 1: Developer: Create a Reserved Core Partition 1.5.2.2. Step 2: Developer: Define a Logic Lock Region 1.5.2.3. Step 3: Developer: Compile and Export the Root Partition 1.5.2.4. Step 4: Consumer: Add the Root Partition and Compile
1.5.4. Viewing Quartus Database File Information x
1.5.4.1. QDB File Attribute Types
1.6. Incremental Block-Based Compilation Flow x
1.6.1. Design Abstraction
1.6.1. Design Abstraction x
1.6.1.1. Empty Partition Clock Source Preservation
1.7. Setting-Up Team-Based Designs x
1.7.1. Creating a Top-Level Project for a Team-Based Design
1.7.1. Creating a Top-Level Project for a Team-Based Design x
1.7.1.1. Prepare a Design Partition for Project Integration
2. About Functional Safety Separation Design Flow x
2.1. Work Flows 2.2. Design Considerations 2.3. Limitations 2.4. About Functional Safety Separation Design Flow Revision History
2.1. Work Flows x
2.1.1. Design Creation Flow 2.1.2. Design Modification Flow
2.2. Design Considerations x
2.2.1. About Safety Logic Partitions and Logic Lock Regions 2.2.2. Clocks, PLLs and Resets 2.2.3. Routing Across Safety Logic Partitions
2.2.2. Clocks, PLLs and Resets x
2.2.2.1. Clocks in Safety Designs
2.2.3. Routing Across Safety Logic Partitions x
2.2.3.1. Routing to Preserve Safety Partitions
3. Implementing Partitions for the Safety Separation Design Flow x
3.1. Preserving the Device Resources 3.2. Fixing the Safety Partitions to Logic Lock Regions 3.3. Exporting and Importing Safety Logic Partitions 3.4. I/O Banks in Safety Partitions 3.5. Safety Region Verification Tool 3.6. Implementing Partitions for the Safety Separation Design Flow Revision History
3.4. I/O Banks in Safety Partitions x
3.4.1. Preserving GPIO IP and the I/Os in I/O Banks in Safety Partitions 3.4.2. Preserving IOPLL IP in I/O Banks in Safety Partitions 3.4.3. Preserving I/Os (other than GPIO IP I/Os) in I/O Banks in Safety Partitions 3.4.4. Verifying the Preserved I/Os in the Safety Partition 3.4.5. HSIO Bank 3A in a Safety Partition
Answers to Top FAQs
1. Block-Based Design Flows
2. About Functional Safety Separation Design Flow
3. Implementing Partitions for the Safety Separation Design Flow
4. Quartus® Prime Pro Edition User Guide: Block-Based Design Document Archive
A. Quartus® Prime Pro Edition User Guides

2.2.1. About Safety Logic Partitions and Logic Lock Regions

Altera recommends that you do not overlap any reserved Logic Lock regions. The Quartus® Prime Fitter does not use overlapping areas. The chip planner checks for overlapping regions.

A design may contain many safety partitions. However, do not create a safety partition within another safety partition. The Quartus® Prime Pro Edition software does not allow hierarchical safety partitions. The design creation flow detects this failure.

If you select an unsupported device for a design containing safety logic partitions, Quartus Prime gives an error during compilation. The error informs you that Safety IP is unsupported for devices other than Agilex 5.

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