1. Agilex™ 7 Embedded Memory Overview
2. Agilex™ 7 Embedded Memory Architecture and Features
3. Agilex™ 7 Embedded Memory Design Considerations
4. Agilex™ 7 Embedded Memory IP References
5. Agilex™ 7 Embedded Memory Debugging
6. Agilex™ 7 Embedded Memory User Guide Archives
7. Document Revision History for the Agilex™ 7 Embedded Memory User Guide
2.1. Fabric Network-On-Chip (NoC) in Agilex™ 7 M-Series M20K Blocks
2.2. Byte Enable in Agilex™ 7 Embedded Memory Blocks
2.3. Address Clock Enable Support
2.4. Asynchronous Clear and Synchronous Clear
2.5. Memory Blocks Error Correction Code (ECC) Support
2.6. Agilex™ 7 Embedded Memory Clocking Modes
2.7. Agilex™ 7 Embedded Memory Configurations
2.8. Force-to-Zero
2.9. Coherent Read Memory
2.10. Freeze Logic
2.11. True Dual Port Dual Clock Emulator
2.12. Initial Value of Read and Write Address Registers
2.13. Timing/Power Optimization Feature in M20K Blocks
2.14. Agilex™ 7 Supported Embedded Memory IPs
3.1. Consider the Memory Block Selection
3.2. Consider the Concurrent Read Behavior
3.3. Read-During-Write (RDW)
3.4. Consider Power-Up State and Memory Initialization
3.5. Reduce Power Consumption
3.6. Avoid Providing Non-Deterministic Input
3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously
3.8. Advanced Settings in Quartus® Prime Software for Memory
3.9. Consider the Memory Depth Setting
3.10. M20K Embedded Memory Block Input Clock Quality Requirement
3.11. Consider Registering the Memory Output
4.1.1. Release Information for RAM and ROM IPs
4.1.2. RAM: 1-PORT FPGA IP Parameters
4.1.3. RAM: 2-PORT FPGA IP Parameters
4.1.4. RAM: 4-PORT FPGA IP Parameters
4.1.5. ROM: 1-PORT FPGA IP Parameters
4.1.6. ROM: 2-PORT FPGA IP Parameters
4.1.7. Changing Parameter Settings Manually
4.1.8. RAM and ROM Interface Signals
4.3.1. Release Information for FIFO IP
4.3.2. Configuration Methods
4.3.3. Specifications
4.3.4. FIFO Functional Timing Requirements
4.3.5. SCFIFO ALMOST_EMPTY Functional Timing
4.3.6. FIFO Output Status Flag and Latency
4.3.7. FIFO Metastability Protection and Related Options
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect
4.3.9. SCFIFO and DCFIFO Show-Ahead Mode
4.3.10. Different Input and Output Width
4.3.11. DCFIFO Timing Constraint Setting
4.3.12. Coding Example for Manual Instantiation
4.3.13. Gray-Code Counter Transfer at the Clock Domain Crossing
4.3.14. Guidelines for Embedded Memory ECC Feature
4.3.15. FIFO IP Parameters
4.3.16. Reset Scheme
4.1.7.1. RAM and ROM Parameter Settings
Name | Legal Values | Description |
---|---|---|
operation_mode | SINGLE_PORT DUAL_PORT BIDIR_DUAL_PORT QUAD_PORT ROM |
Operation mode of the memory block. |
width_a | — | Data width of port A. |
widthad_a | — | Address width of port A. |
numwords_a | — | Number of data words in the memory block for port A. |
outdata_reg_a | UNREGISTERED CLOCK1 CLOCK0 |
Clock for the data output registers of port A. |
outdata_aclr_a | NONE CLEAR1 CLEAR0 |
Asynchronous clear for data output registers of port A. When the outdata_reg_a parameter is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch. |
address_aclr_a | NONE CLEAR0 |
Option to clear the address input registers of port A. |
width_byteena_a | — | Width of the byte-enable bus of port A. The width must be equal to the value of width_a divided by the byte size. The default value of 1 is only allowed when byte-enable is not used. |
width_b | — | Data width of port B. |
widthad_b | — | Address width of port B. |
numwords_b | — | Number of data words in the memory block for port B. |
outdata_reg_b | UNREGISTERED CLOCK1 CLOCK0 |
Clock for the data output registers of port B. |
address_reg_b | CLOCK1 CLOCK0 |
Clock for the address registers of port B. |
outdata_aclr_b | NONE CLEAR1 CLEAR0 |
Asynchronous clear for data output registers of port B. When the outdata_reg_b parameter is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch. |
address_aclr_b | NONE CLEAR0 |
Option to clear the address input registers of port B. |
width_byteena_b | — | Width of the byte-enable bus of port B. The width must be equal to the value of width_b divided by the byte size. The default value of 1 is only allowed when byte-enable is not used. |
intended_device_family | “Agilex 7” |
Parameter used for simulation purpose. |
ram_block_type | AUTO M20K MLAB |
The memory block type. |
byte_size | 5 8 9 10 |
The byte size for the byte-enable mode. |
read_during_write_mode_mixed_ports | DONT_CARE CONSTRAINT_DONT_CARE NEW_DATA OLD_DATA NEW_A_OLD_B |
The behavior for the read-during-write mode.
|
init_file | *.mif *.hex |
The initialization file. |
init_file_layout | PORT_A PORT_B |
The layout of the initialization file. |
maximum_depth | — | The depth of the memory block slices. |
clock_enable_input_a | NORMAL BYPASS |
The clock enable for the input registers of port A. |
clock_enable_output_a | NORMAL BYPASS |
The clock enable for the output registers of port A. |
clock_enable_input_b | NORMAL BYPASS |
The clock enable for the input registers of port B. |
clock_enable_output_b | NORMAL BYPASS |
The clock enable for the output registers of port B. |
read_during_write_mode_port_a | NEW_DATA_NO_NBE_READ NEW_DATA_WITH_NBE_READ OLD_DATA DONT_CARE |
The read-during-write behavior for port A. |
read_during_write_mode_port_b | NEW_DATA_NO_NBE_READ NEW_DATA_WITH_NBE_READ OLD_DATA DONT_CARE |
The read-during-write behavior for port B. |
enable_ecc | TRUE FALSE |
Enables or disables the ECC feature. |
ecc_pipeline_stage_enabled | TRUE FALSE |
|
enable_ecc_encoder_bypass | TRUE FALSE |
Enables or disables the ECC Encoder Bypass feature.
|
enable_coherent_read | TRUE FALSE |
Enables or disables the coherent read feature.
|
enable_force_to_zero | TRUE FALSE |
Enables or disables the Force-to-Zero feature.
|
optimization_option | AUTO HIGH_SPEED 13 LOW_POWER |
Specifies how the RAM block would be optimized.
|