Agilex™ 7 Embedded Memory User Guide

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ID 683241
Date 7/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Embedded Memory Overview 2. Agilex™ 7 Embedded Memory Architecture and Features 3. Agilex™ 7 Embedded Memory Design Considerations 4. Agilex™ 7 Embedded Memory IP References 5. Agilex™ 7 Embedded Memory Debugging 6. Agilex™ 7 Embedded Memory User Guide Archives 7. Document Revision History for the Agilex™ 7 Embedded Memory User Guide
1. Agilex™ 7 Embedded Memory Overview x
1.1. Agilex™ 7 Embedded Memory Features
2. Agilex™ 7 Embedded Memory Architecture and Features x
2.1. Fabric Network-On-Chip (NoC) in Agilex™ 7 M-Series M20K Blocks 2.2. Byte Enable in Agilex™ 7 Embedded Memory Blocks 2.3. Address Clock Enable Support 2.4. Asynchronous Clear and Synchronous Clear 2.5. Memory Blocks Error Correction Code (ECC) Support 2.6. Agilex™ 7 Embedded Memory Clocking Modes 2.7. Agilex™ 7 Embedded Memory Configurations 2.8. Force-to-Zero 2.9. Coherent Read Memory 2.10. Freeze Logic 2.11. True Dual Port Dual Clock Emulator 2.12. Initial Value of Read and Write Address Registers 2.13. Timing/Power Optimization Feature in M20K Blocks 2.14. Agilex™ 7 Supported Embedded Memory IPs
2.2. Byte Enable in Agilex™ 7 Embedded Memory Blocks x
2.2.1. Byte Enable Controls 2.2.2. Data Byte Output 2.2.3. Byte Enable Behavior
2.5. Memory Blocks Error Correction Code (ECC) Support x
2.5.1. Error Correction Code Truth Table 2.5.2. Parity Bit 2.5.3. ECC Parity Flip 2.5.4. ECC Read-During-Write Behavior
2.6. Agilex™ 7 Embedded Memory Clocking Modes x
2.6.1. Single Clock Mode 2.6.2. Read/Write Clock Mode 2.6.3. Input/Output Clock Mode 2.6.4. Asynchronous/Synchronous Clears in Clocking Modes 2.6.5. Output Read Data in Simultaneous Read/Write 2.6.6. Independent Clock Enables in Clocking Modes
2.7. Agilex™ 7 Embedded Memory Configurations x
2.7.1. Mixed-Width Port Configurations
2.9. Coherent Read Memory x
2.9.1. Forwarding Logic
2.11. True Dual Port Dual Clock Emulator x
2.11.1. True Dual-Port Mixed Port Read During Write New Data Emulation
3. Agilex™ 7 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Read Behavior 3.3. Read-During-Write (RDW) 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Advanced Settings in Quartus® Prime Software for Memory 3.9. Consider the Memory Depth Setting 3.10. M20K Embedded Memory Block Input Clock Quality Requirement 3.11. Consider Registering the Memory Output
3.3. Read-During-Write (RDW) x
3.3.1. Customize Read-During-Write Behavior
3.3.1. Customize Read-During-Write Behavior x
3.3.1.1. Same-Port Read-During-Write Mode 3.3.1.2. Mixed-Port Read-During-Write Mode
4. Agilex™ 7 Embedded Memory IP References x
4.1. On-Chip Memory RAM and ROM IPs 4.2. eSRAM Agilex™ FPGA IP 4.3. FIFO IP 4.4. Shift Register (RAM-based) FPGA IP
4.1. On-Chip Memory RAM and ROM IPs x
4.1.1. Release Information for RAM and ROM IPs 4.1.2. RAM: 1-PORT FPGA IP Parameters 4.1.3. RAM: 2-PORT FPGA IP Parameters 4.1.4. RAM: 4-PORT FPGA IP Parameters 4.1.5. ROM: 1-PORT FPGA IP Parameters 4.1.6. ROM: 2-PORT FPGA IP Parameters 4.1.7. Changing Parameter Settings Manually 4.1.8. RAM and ROM Interface Signals
4.1.7. Changing Parameter Settings Manually x
4.1.7.1. RAM and ROM Parameter Settings
4.2. eSRAM Agilex™ FPGA IP x
4.2.1. Release Information for eSRAM Agilex™ FPGA IP 4.2.2. eSRAM System Features 4.2.3. eSRAM Agilex™ FPGA IP Parameters 4.2.4. eSRAM Agilex™ FPGA IP Interface Signals 4.2.5. eSRAM Timing Diagrams
4.2.2. eSRAM System Features x
4.2.2.1. eSRAM Specifications
4.3. FIFO IP x
4.3.1. Release Information for FIFO IP 4.3.2. Configuration Methods 4.3.3. Specifications 4.3.4. FIFO Functional Timing Requirements 4.3.5. SCFIFO ALMOST_EMPTY Functional Timing 4.3.6. FIFO Output Status Flag and Latency 4.3.7. FIFO Metastability Protection and Related Options 4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect 4.3.9. SCFIFO and DCFIFO Show-Ahead Mode 4.3.10. Different Input and Output Width 4.3.11. DCFIFO Timing Constraint Setting 4.3.12. Coding Example for Manual Instantiation 4.3.13. Gray-Code Counter Transfer at the Clock Domain Crossing 4.3.14. Guidelines for Embedded Memory ECC Feature 4.3.15. FIFO IP Parameters 4.3.16. Reset Scheme
4.3.3. Specifications x
4.3.3.1. Verilog HDL Prototype 4.3.3.2. VHDL Component Declaration 4.3.3.3. VHDL LIBRARY-USE Declaration 4.3.3.4. HDL Code from Parameterizable Macros Template 4.3.3.5. FIFO Signals 4.3.3.6. FIFO Parameter Settings
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.3.8.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.3.11. DCFIFO Timing Constraint Setting x
4.3.11.1. Embedded Timing Constraint 4.3.11.2. User Configurable Timing Constraint
4.3.11.2. User Configurable Timing Constraint x
4.3.11.2.1. SDC Commands
4.4. Shift Register (RAM-based) FPGA IP x
4.4.1. Release Information for Shift Register (RAM-based) FPGA IP 4.4.2. Shift Register (RAM-based) FPGA IP 4.4.3. Shift Register (RAM-based) FPGA IP General Description 4.4.4. Shift Register (RAM-based) FPGA IP Parameter Settings 4.4.5. Shift Register Ports and Parameters Setting
1. Agilex™ 7 Embedded Memory Overview
2. Agilex™ 7 Embedded Memory Architecture and Features
3. Agilex™ 7 Embedded Memory Design Considerations
4. Agilex™ 7 Embedded Memory IP References
5. Agilex™ 7 Embedded Memory Debugging
6. Agilex™ 7 Embedded Memory User Guide Archives
7. Document Revision History for the Agilex™ 7 Embedded Memory User Guide

4.3.11.2.1. SDC Commands

Table 75.  SDC Commands usage in the Quartus® Prime Fitter and Timing Analyzer These SDC descriptions provided are overview for DCFIFO use case. For the exact SDC details, refer to the Quartus® Prime Timing Analyzer chapter in the Quartus® Prime Pro Edition Handbook.
SDC Command Fitter Timing Analyzer Recommended Settings
set_max_skew 42 To constraint placement and routing of flops in the multi-bit CDC paths to meet the specified skew requirement among bits.

To analyze whether the specified skew requirement is fully met. Both clock and data paths are taken into consideration.

Set to less than 1 launch clock.
set_net_delay

Similar to set_max_skew but without taking clock skews into considerations.

To ensure the crossing latency is bounded.

To analyze whether the specified net delay requirement is fully met. Clock paths are not taken into consideration.

This is currently set to be less than 1 latch clock. 43
set_min_delay/set_max_delay

To relax fitter effort by mimicking the set_false_path command but without overriding other SDCs. 44

To relax timing analysis for the setup/hold checks to not fail. 45

This is currently set to 100ns/-100ns for max/min. 46
42 It can have significant compilation time impact in older Quartus versions without Timing Analyzer 2.
43 For advanced users, you can fine-tune the value based on your design. For instance, if the designs are able to tolerate longer crossing latency (full and empty status can be delayed), this can be relaxed.
44 Without set_false_path (which has the highest precedence and may result in very long insertion delays), Fitter attempts to meet the default setup/hold which is extremely over constraint.
45 Without set_false_path, the CDC paths will be analyzed for default setup/hold, which is extremely over constraint.
46 Expect an approximately 100 ns delay when you observe CDC paths compared to set_false_path.
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