1. Agilex™ 7 Embedded Memory Overview
2. Agilex™ 7 Embedded Memory Architecture and Features
3. Agilex™ 7 Embedded Memory Design Considerations
4. Agilex™ 7 Embedded Memory IP References
5. Agilex™ 7 Embedded Memory Debugging
6. Agilex™ 7 Embedded Memory User Guide Archives
7. Document Revision History for the Agilex™ 7 Embedded Memory User Guide
2.1. Fabric Network-On-Chip (NoC) in Agilex™ 7 M-Series M20K Blocks
2.2. Byte Enable in Agilex™ 7 Embedded Memory Blocks
2.3. Address Clock Enable Support
2.4. Asynchronous Clear and Synchronous Clear
2.5. Memory Blocks Error Correction Code (ECC) Support
2.6. Agilex™ 7 Embedded Memory Clocking Modes
2.7. Agilex™ 7 Embedded Memory Configurations
2.8. Force-to-Zero
2.9. Coherent Read Memory
2.10. Freeze Logic
2.11. True Dual Port Dual Clock Emulator
2.12. Initial Value of Read and Write Address Registers
2.13. Timing/Power Optimization Feature in M20K Blocks
2.14. Agilex™ 7 Supported Embedded Memory IPs
3.1. Consider the Memory Block Selection
3.2. Consider the Concurrent Read Behavior
3.3. Read-During-Write (RDW)
3.4. Consider Power-Up State and Memory Initialization
3.5. Reduce Power Consumption
3.6. Avoid Providing Non-Deterministic Input
3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously
3.8. Advanced Settings in Quartus® Prime Software for Memory
3.9. Consider the Memory Depth Setting
3.10. M20K Embedded Memory Block Input Clock Quality Requirement
3.11. Consider Registering the Memory Output
4.1.1. Release Information for RAM and ROM IPs
4.1.2. RAM: 1-PORT FPGA IP Parameters
4.1.3. RAM: 2-PORT FPGA IP Parameters
4.1.4. RAM: 4-PORT FPGA IP Parameters
4.1.5. ROM: 1-PORT FPGA IP Parameters
4.1.6. ROM: 2-PORT FPGA IP Parameters
4.1.7. Changing Parameter Settings Manually
4.1.8. RAM and ROM Interface Signals
4.3.1. Release Information for FIFO IP
4.3.2. Configuration Methods
4.3.3. Specifications
4.3.4. FIFO Functional Timing Requirements
4.3.5. SCFIFO ALMOST_EMPTY Functional Timing
4.3.6. FIFO Output Status Flag and Latency
4.3.7. FIFO Metastability Protection and Related Options
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect
4.3.9. SCFIFO and DCFIFO Show-Ahead Mode
4.3.10. Different Input and Output Width
4.3.11. DCFIFO Timing Constraint Setting
4.3.12. Coding Example for Manual Instantiation
4.3.13. Gray-Code Counter Transfer at the Clock Domain Crossing
4.3.14. Guidelines for Embedded Memory ECC Feature
4.3.15. FIFO IP Parameters
4.3.16. Reset Scheme
2.5. Memory Blocks Error Correction Code (ECC) Support
ECC detects and corrects data errors at the output of the memory.
Only M20K blocks and eSRAM blocks support the ECC feature.
If you engage the ECC feature, you cannot use the following features:
- Byte enable
- Coherent read
- Mixed data width
M20K Blocks
For M20K blocks, ECC performs single-error correction, double-adjacent-error correction, and triple-adjacent-error correction in a 32-bit word. However, ECC cannot guarantee detection or correction of non-adjacent two-bit or more errors.
The M20K blocks have built-in support for ECC when in ×32-wide simple dual-port mode.
- When you engage the ECC feature, the M20K runs slower than the non-ECC simple dual-port mode. However, you can enable optional ECC pipeline registers before the output decoder to achieve higher performance compared to non-pipeline ECC mode at the expense of one-cycle latency.
- Two ECC status flag signals—e (error) and ue (uncorrectable error) indicate the M20K ECC status. The status flags are part of the regular outputs from the memory block.
eSRAM Blocks
For eSRAM blocks, ECC performs single-error correction and double-error detection in a 64-bit word.
The eSRAM blocks have built-in support for ECC when in ×64-wide simple dual-port mode.
- Two ECC status flag signals— p{0..3}_eccflags[1] (error corrected) and p{0..3}_eccflags[0] (error detected) indicate the eSRAM ECC status.