Agilex™ 7 Embedded Memory User Guide

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ID 683241
Date 4/15/2025
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Embedded Memory Overview 2. Agilex™ 7 Embedded Memory Architecture and Features 3. Agilex™ 7 Embedded Memory Design Considerations 4. Agilex™ 7 Embedded Memory IP References 5. Agilex™ 7 Embedded Memory Debugging 6. Agilex™ 7 Embedded Memory User Guide Archives 7. Document Revision History for the Agilex™ 7 Embedded Memory User Guide
1. Agilex™ 7 Embedded Memory Overview x
1.1. Agilex™ 7 Embedded Memory Features
2. Agilex™ 7 Embedded Memory Architecture and Features x
2.1. Fabric Network-On-Chip (NoC) in Agilex™ 7 M-Series M20K Blocks 2.2. Byte Enable in Agilex™ 7 Embedded Memory Blocks 2.3. Address Clock Enable Support 2.4. Asynchronous Clear and Synchronous Clear 2.5. Memory Blocks Error Correction Code (ECC) Support 2.6. Agilex™ 7 Embedded Memory Clocking Modes 2.7. Agilex™ 7 Embedded Memory Configurations 2.8. Force-to-Zero 2.9. Coherent Read Memory 2.10. Freeze Logic 2.11. True Dual Port Dual Clock Emulator 2.12. Initial Value of Read and Write Address Registers 2.13. Timing/Power Optimization Feature in M20K Blocks 2.14. Agilex™ 7 Supported Embedded Memory IPs
2.2. Byte Enable in Agilex™ 7 Embedded Memory Blocks x
2.2.1. Byte Enable Controls 2.2.2. Data Byte Output 2.2.3. Byte Enable Behavior
2.5. Memory Blocks Error Correction Code (ECC) Support x
2.5.1. Error Correction Code Truth Table 2.5.2. Parity Bit 2.5.3. ECC Parity Flip 2.5.4. ECC Read-During-Write Behavior
2.6. Agilex™ 7 Embedded Memory Clocking Modes x
2.6.1. Single Clock Mode 2.6.2. Read/Write Clock Mode 2.6.3. Input/Output Clock Mode 2.6.4. Asynchronous/Synchronous Clears in Clocking Modes 2.6.5. Output Read Data in Simultaneous Read/Write 2.6.6. Independent Clock Enables in Clocking Modes
2.7. Agilex™ 7 Embedded Memory Configurations x
2.7.1. Mixed-Width Port Configurations
2.9. Coherent Read Memory x
2.9.1. Forwarding Logic
3. Agilex™ 7 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Read Behavior 3.3. Read-During-Write (RDW) 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Advanced Settings in Quartus® Prime Software for Memory 3.9. Consider the Memory Depth Setting 3.10. M20K Embedded Memory Block Input Clock Quality Requirement 3.11. Consider Registering the Memory Output
3.3. Read-During-Write (RDW) x
3.3.1. Customize Read-During-Write Behavior
3.3.1. Customize Read-During-Write Behavior x
3.3.1.1. Same-Port Read-During-Write Mode 3.3.1.2. Mixed-Port Read-During-Write Mode
4. Agilex™ 7 Embedded Memory IP References x
4.1. On-Chip Memory RAM and ROM FPGA IPs 4.2. eSRAM Agilex™ FPGA IP 4.3. FIFO Intel FPGA IP 4.4. Shift Register (RAM-based) FPGA IP
4.1. On-Chip Memory RAM and ROM FPGA IPs x
4.1.1. Release Information for RAM and ROM IPs 4.1.2. RAM: 1-PORT FPGA IP Parameters 4.1.3. RAM: 2-PORT FPGA IP Parameters 4.1.4. RAM: 4-PORT FPGA IP Parameters 4.1.5. ROM: 1-PORT FPGA IP Parameters 4.1.6. ROM: 2-PORT FPGA IP Parameters 4.1.7. Changing Parameter Settings Manually 4.1.8. RAM and ROM Interface Signals
4.1.7. Changing Parameter Settings Manually x
4.1.7.1. RAM and ROM Parameter Settings
4.2. eSRAM Agilex™ FPGA IP x
4.2.1. Release Information for eSRAM Agilex™ FPGA IP 4.2.2. eSRAM System Features 4.2.3. eSRAM Agilex™ FPGA IP Parameters 4.2.4. eSRAM Agilex™ FPGA IP Interface Signals 4.2.5. eSRAM Timing Diagrams
4.2.2. eSRAM System Features x
4.2.2.1. eSRAM Specifications
4.3. FIFO Intel FPGA IP x
4.3.1. Release Information for FIFO Intel FPGA IP 4.3.2. Configuration Methods 4.3.3. Specifications 4.3.4. FIFO Functional Timing Requirements 4.3.5. SCFIFO ALMOST_EMPTY Functional Timing 4.3.6. FIFO Output Status Flag and Latency 4.3.7. FIFO Metastability Protection and Related Options 4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect 4.3.9. SCFIFO and DCFIFO Show-Ahead Mode 4.3.10. Different Input and Output Width 4.3.11. DCFIFO Timing Constraint Setting 4.3.12. Coding Example for Manual Instantiation 4.3.13. Gray-Code Counter Transfer at the Clock Domain Crossing 4.3.14. Guidelines for Embedded Memory ECC Feature 4.3.15. FIFO Intel FPGA IP Parameters 4.3.16. Reset Scheme
4.3.3. Specifications x
4.3.3.1. Verilog HDL Prototype 4.3.3.2. VHDL Component Declaration 4.3.3.3. VHDL LIBRARY-USE Declaration 4.3.3.4. HDL Code from Parameterizable Macros Template 4.3.3.5. FIFO Signals 4.3.3.6. FIFO Parameter Settings
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.3.8.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.3.11. DCFIFO Timing Constraint Setting x
4.3.11.1. Embedded Timing Constraint 4.3.11.2. User Configurable Timing Constraint
4.3.11.2. User Configurable Timing Constraint x
4.3.11.2.1. SDC Commands
4.4. Shift Register (RAM-based) FPGA IP x
4.4.1. Release Information for Shift Register (RAM-based) FPGA IP 4.4.2. Shift Register (RAM-based) FPGA IP 4.4.3. Shift Register (RAM-based) FPGA IP General Description 4.4.4. Shift Register (RAM-based) FPGA IP Parameter Settings 4.4.5. Shift Register Ports and Parameters Setting
1. Agilex™ 7 Embedded Memory Overview
2. Agilex™ 7 Embedded Memory Architecture and Features
3. Agilex™ 7 Embedded Memory Design Considerations
4. Agilex™ 7 Embedded Memory IP References
5. Agilex™ 7 Embedded Memory Debugging
6. Agilex™ 7 Embedded Memory User Guide Archives
7. Document Revision History for the Agilex™ 7 Embedded Memory User Guide

4.1.6. ROM: 2-PORT FPGA IP Parameters

Table 48.   ROM: 2-PORT FPGA IP Parameters—General
Parameter Legal Values Description
Use different data widths on different ports On/Off Specifies whether to use different data widths on different ports.
Table 49.   ROM: 2-PORT FPGA IP Parameters—Widths/Blk Type Tab
Parameter Legal Values Description
How many bits of memory? —

Specifies the memory size in number of bits.

This parameter is available if Type is As a number of bits.

Type
  • As a number of words
  • As a number of bits
Determines whether to specify the memory size in words or bits.
How many words of memory? 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, or 65536

Specifies the number of words.

This parameter is available if Type is As a number of words.

How wide should the 'q_a' output bus be? — Specifies the width of the 'q_a' and 'q_b' output ports.
How wide should the 'q_b' output bus be?
Ram Block Type
  • Auto
  • M20K
Specifies the memory block type. The types of memory block that are available for selection depends on your target device
Set the maximum block depth to
  • Auto: Auto, 512, 1024, or 2048
  • M20K: Auto, 512, 1024, or 2048
Specifies the maximum block depth in words.
Table 50.   ROM: 2-PORT FPGA IP Parameters—Clks/Rd Tab
Parameter Legal Values Description
Type

Specifies the clocking method to use.

  • Single—A single clock and a clock enable controls all registers of the memory block
  • Dual clock: use separate 'input' and 'output' clocks—The input clock controls the address registers and the output clock controls the data-out registers. There are no write-enable, byte-enable, or data-in registers in ROM mode.
  • Customize clocks for A and B ports—Clock A controls all registers on the port A side; clock B controls all registers on the port B side. Each port also supports independent clock enables for both port A and port B registers, respectively.
Create a 'rden_a' and 'rden_b' read enable signals On/Off Specifies whether to create read enable signals.
Table 51.   ROM: 2-PORT FPGA IP Parameters—Regs/Clkens/Aclrs Tab
Parameter Legal Values Description

Read output ports

 On/Off Specifies whether to register the read output ports.
Registered Q Output Ports 'q_a' port On/Off Turn on if you want the registered 'q_a' and 'q_b' ports to be affected by the asynchronous clear signal.
  • q_a port—specifies whether to register the 'q_b' output port.
  • q_b port—specifies whether to register the 'q_b' output port.
'q_b' port
Use clock enable for port A input registers On/Off Specifies whether to use clock enable for port A input registers.
Use clock enable for port A output registers On/Off Specifies whether to use clock enable for port A output registers.
Use clock enable for port B input registers On/Off Specifies whether to use clock enable for port B input registers.
Use clock enable for port B output registers On/Off Specifies whether to use clock enable for port B output registers.
Aclr Options 'q_a' port On/Off Specifies whether the registered ports should be cleared by the asynchronous clear port.
'q_b' port
Sclr Options 'q_a' port On/Off Specifies whether the registered ports should be cleared by the synchronous clear port.
'q_b' port
Table 52.   ROM: 2-PORT FPGA IP Parameters—Mem Init Tab
Parameter Legal Values Description
Type
  • No, leave it blank
  • Yes, use this file for the memory content data

Specifies the initial content of the memory.

In ROM mode, you must specify a memory initialization file (.mif) or a hexadecimal (Altera-format) file (.hex). The Yes, use this file for the memory content data option is turned on by default.

File name — Specify a file name if initial content of the memory is not set to blank. The file must be in .hex or .mif format.
The initial content file should conform to which port's dimensions?
  • PORT_A
  • PORT_B
Specifies whether the initial content file conforms to port A or port B.
Table 53.   ROM: 2-PORT FPGA IP Parameters—Performance Optimization Tab
Parameter Legal Values Description
Enable Force-to-Zero On/Off Specifies whether to set the output to zero when you deassert the read enable signal.

Enabling this feature helps improve the glue logic performance when the selected memory depth is larger than a single memory block.

Which timing/power optimization option do you want to use?
  • Auto
  • High Speed 12
  • Low Power
Specifies the timing/power optimization option to use. This option is only applicable when you select M20K memory type on Agilex™ 7 devices.
12 For Agilex™ 7 M-Series, only HIGH_SPEED option is available.
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