Intel Agilex® 7 Embedded Memory User Guide

ID 683241
Date 6/26/2023

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2.11. True Dual Port Dual Clock Emulator

The true dual port (TDP) dual clock emulator feature emulates a TDP dual clock mode. This feature provides backward compatibility with Intel® Arria® 10 devices, which supports TDP dual clock mode.

This feature is supported only in the following conditions:

  • Two read/write ports operation mode.
  • Customize clocks for A and B ports clocking mode.
Note: You must turn on Emulate TDP dual clock mode to enable the TDP dual clock emulator feature in the parameter editors of the dual-port RAM IP core. Refer to RAM: 2-PORT Intel FPGA IP Parameter Settings for more information about how to enable this feature.

The TDP dual clock emulator consists of two DCFIFOs and a single RAM block. The DCFIFO handles clock domain crossing (CDC) issues for the control signals and is a temporary buffer for data storage before and after being processed by the RAM block.

Due to the non-deterministic latency caused by different clock frequencies, a valid signal is introduced to identify whether the output data is valid. When the valid signal is asserted, it indicates that you should adhere to the correct output data. If the valid signal is de-asserted, discard the output data.

The clock connection to Port A must be a slow clock (clock A) and the clock connection to Port B must be a fast clock (clock B), with a clock frequency ratio of clock B divided by clock A is greater than or equal to seven.

The DCFIFO depth follows the RAM depth that is set in the dual-port RAM IP. You may change the DCFIFO depth manually through the design file after the HDL generation in the RAM IP Parameter Editor. The DCFIFO depth must be greater than the clock frequency ratio of clock B divided by clock A to ensure the emulated TDP dual clock mode works properly. For example, if the ratio of Clock B frequency/Clock A frequency is 10, the minimum DCFIFO depth must be 16 (2^4) or above.

When you engage the TDP dual clock emulator feature, port A and port B will have different latency. The latency for port A decreases as the difference between the two clock frequencies increase, with a minimum latency of five clock cycles. Port B latency is fixed to two clock cycles, with the output registers always enabled for this configuration.

The following figures show the timing diagrams for the TDP dual clock emulator feature.

Figure 16. Output Condition of Port A
Figure 17. Output Condition of Port B
Figure 18. Read-During-Write Condition of Port A
Figure 19. Read-During-Write Condition of Port B