Intel Agilex® 7 Embedded Memory User Guide

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ID 683241
Date 6/26/2023
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Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 Embedded Memory Overview 2. Intel Agilex® 7 Embedded Memory Architecture and Features 3. Intel Agilex® 7 Embedded Memory Design Considerations 4. Intel Agilex® 7 Embedded Memory IP References 5. Intel Agilex® 7 Embedded Memory Debugging 6. Intel Agilex® 7 Embedded Memory User Guide Archives 7. Document Revision History for the Intel Agilex® 7 Embedded Memory User Guide
1. Intel Agilex® 7 Embedded Memory Overview x
1.1. Intel Agilex® 7 Embedded Memory Features
2. Intel Agilex® 7 Embedded Memory Architecture and Features x
2.1. Fabric Network-On-Chip (NoC) in Intel Agilex® 7 M-Series M20K Blocks 2.2. Byte Enable in Intel Agilex® 7 Embedded Memory Blocks 2.3. Address Clock Enable Support 2.4. Asynchronous Clear and Synchronous Clear 2.5. Memory Blocks Error Correction Code (ECC) Support 2.6. Intel Agilex® 7 Embedded Memory Clocking Modes 2.7. Intel Agilex® 7 Embedded Memory Configurations 2.8. Force-to-Zero 2.9. Coherent Read Memory 2.10. Freeze Logic 2.11. True Dual Port Dual Clock Emulator 2.12. Initial Value of Read and Write Address Registers 2.13. Timing/Power Optimization Feature in M20K Blocks 2.14. Intel Agilex® 7 Supported Embedded Memory IPs
2.2. Byte Enable in Intel Agilex® 7 Embedded Memory Blocks x
2.2.1. Byte Enable Controls 2.2.2. Data Byte Output 2.2.3. Byte Enable Behavior
2.5. Memory Blocks Error Correction Code (ECC) Support x
2.5.1. Parity Bit 2.5.2. ECC Parity Flip 2.5.3. ECC Read-During-Write Behavior 2.5.4. Error Correction Code Truth Table
2.6. Intel Agilex® 7 Embedded Memory Clocking Modes x
2.6.1. Single Clock Mode 2.6.2. Read/Write Clock Mode 2.6.3. Input/Output Clock Mode 2.6.4. Asynchronous/Synchronous Clears in Clocking Modes 2.6.5. Output Read Data in Simultaneous Read/Write 2.6.6. Independent Clock Enables in Clocking Modes
2.7. Intel Agilex® 7 Embedded Memory Configurations x
2.7.1. Mixed-Width Port Configurations
2.9. Coherent Read Memory x
2.9.1. Forwarding Logic
3. Intel Agilex® 7 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Read Behavior 3.3. Customize Read-During-Write Behavior 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Advanced Settings in Intel® Quartus® Prime Software for Memory 3.9. Consider the Memory Depth Setting 3.10. Consider Registering the Memory Output
3.3. Customize Read-During-Write Behavior x
3.3.1. Same-Port Read-During-Write Mode 3.3.2. Mixed-Port Read-During-Write Mode
4. Intel Agilex® 7 Embedded Memory IP References x
4.1. On Chip Memory RAM and ROM Intel® FPGA IP Cores 4.2. eSRAM Intel Agilex® FPGA IP 4.3. FIFO Intel® FPGA IP 4.4. Shift Register (RAM-based) Intel® FPGA IP
4.1. On Chip Memory RAM and ROM Intel® FPGA IP Cores x
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs 4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters 4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters 4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters 4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters 4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters 4.1.7. Changing Parameter Settings Manually 4.1.8. RAM and ROM Interface Signals
4.1.7. Changing Parameter Settings Manually x
4.1.7.1. RAM and ROM Parameter Settings
4.2. eSRAM Intel Agilex® FPGA IP x
4.2.1. Release Information for eSRAM Intel Agilex® FPGA IP 4.2.2. eSRAM System Features 4.2.3. eSRAM Intel Agilex® FPGA IP Parameters 4.2.4. eSRAM Intel Agilex® FPGA IP Interface Signals 4.2.5. eSRAM Timing Diagrams
4.2.2. eSRAM System Features x
4.2.2.1. eSRAM Specifications
4.3. FIFO Intel® FPGA IP x
4.3.1. Release Information for FIFO Intel® FPGA IP 4.3.2. Configuration Methods 4.3.3. Specifications 4.3.4. FIFO Functional Timing Requirements 4.3.5. SCFIFO ALMOST_EMPTY Functional Timing 4.3.6. FIFO Output Status Flag and Latency 4.3.7. FIFO Metastability Protection and Related Options 4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect 4.3.9. SCFIFO and DCFIFO Show-Ahead Mode 4.3.10. Different Input and Output Width 4.3.11. DCFIFO Timing Constraint Setting 4.3.12. Coding Example for Manual Instantiation 4.3.13. Design Example 4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing 4.3.15. Guidelines for Embedded Memory ECC Feature 4.3.16. FIFO Intel® FPGA IP Parameters 4.3.17. Reset Scheme
4.3.3. Specifications x
4.3.3.1. Verilog HDL Prototype 4.3.3.2. VHDL Component Declaration 4.3.3.3. VHDL LIBRARY-USE Declaration 4.3.3.4. HDL Code from Parameterizable Macros Template 4.3.3.5. FIFO Signals 4.3.3.6. FIFO Parameter Settings
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.3.8.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.3.11. DCFIFO Timing Constraint Setting x
4.3.11.1. Embedded Timing Constraint 4.3.11.2. User Configurable Timing Constraint
4.3.11.2. User Configurable Timing Constraint x
4.3.11.2.1. SDC Commands
4.4. Shift Register (RAM-based) Intel® FPGA IP x
4.4.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP 4.4.2. Shift Register (RAM-based) Intel® FPGA IP Features 4.4.3. Shift Register (RAM-based) Intel® FPGA IP General Description 4.4.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings 4.4.5. Shift Register Ports and Parameters Setting
1. Intel Agilex® 7 Embedded Memory Overview
2. Intel Agilex® 7 Embedded Memory Architecture and Features
3. Intel Agilex® 7 Embedded Memory Design Considerations
4. Intel Agilex® 7 Embedded Memory IP References
5. Intel Agilex® 7 Embedded Memory Debugging
6. Intel Agilex® 7 Embedded Memory User Guide Archives
7. Document Revision History for the Intel Agilex® 7 Embedded Memory User Guide

4.3.7. FIFO Metastability Protection and Related Options

The FIFO Intel® FPGA IP parameter editor provides the total latency, clock synchronization, metastability protection, area, and fMAX options as a group setting for the DCFIFO.
Table 45.  DCFIFO Group Setting for Latency and Related Options This table shows the available group setting.
Group Setting Comment
Lowest latency but requires synchronized clocks This option uses one synchronization stage with no metastability protection. It uses the smallest size and provides good fMAX.

Select this option if the read and write clocks are related clocks.
Minimal setting for unsynchronized clocks This option uses two synchronization stages with good metastability protection. It uses the medium size and provides good fMAX.
Best metastability protection, best fmax and unsynchronized clocks This option uses three or more synchronization stages with the best metastability protection. It uses the largest size but gives the best fMAX.

The group setting for latency and related options is available through the FIFO Intel® FPGA IP parameter editor. The setting mainly determines the number of synchronization stages, depending on the group setting you select. You can also set the number of synchronization stages you desire through the WRSYNC_DELAYPIPE and RDSYNC_DELAYPIPE parameters, but you must understand how the actual number of synchronization stages relates to the parameter values set in different target devices.

The number of synchronization stages set is related to the value of the WRSYNC_DELAYPIPE and RDSYNC_DELAYPIPE pipeline parameters. For some cases, these pipeline parameters are internally scaled down by two to reflect the actual synchronization stage.

The following equation shows the relationship between the actual synchronization stage and the pipeline parameters:

Actual synchronization stage = value of pipeline parameter - 2

Note: The values assigned to WRSYNC_DELAYPIPE and RDSYNC_DELAYPIPE parameters are internally reduced by 2 to represent the actual synchronization stage implemented. Thus, the default value 3 for these parameters corresponds to a single synchronization pipe stage; a value of 4 results in 2 synchronization stages, and so on. Choose 4 (2 synchronization stages) for metastability protection.

The Timing Analyzer includes the capability to estimate the robustness of asynchronous transfers in your design, and to generate a report that details the mean time between failures (MTBF) for all detected synchronization register chains. This report includes the MTBF analysis on the synchronization pipeline you applied between the asynchronous clock domains in your DCFIFO. You can then decide the number of synchronization stages to use in order to meet the range of the MTBF specification you require.

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