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1. Intel Agilex® 7 Embedded Memory Overview
2. Intel Agilex® 7 Embedded Memory Architecture and Features
3. Intel Agilex® 7 Embedded Memory Design Considerations
4. Intel Agilex® 7 Embedded Memory IP References
5. Intel Agilex® 7 Embedded Memory Debugging
6. Intel Agilex® 7 Embedded Memory User Guide Archives
7. Document Revision History for the Intel Agilex® 7 Embedded Memory User Guide
2.1. Fabric Network-On-Chip (NoC) in Intel Agilex® 7 M-Series M20K Blocks
2.2. Byte Enable in Intel Agilex® 7 Embedded Memory Blocks
2.3. Address Clock Enable Support
2.4. Asynchronous Clear and Synchronous Clear
2.5. Memory Blocks Error Correction Code (ECC) Support
2.6. Intel Agilex® 7 Embedded Memory Clocking Modes
2.7. Intel Agilex® 7 Embedded Memory Configurations
2.8. Force-to-Zero
2.9. Coherent Read Memory
2.10. Freeze Logic
2.11. True Dual Port Dual Clock Emulator
2.12. Initial Value of Read and Write Address Registers
2.13. Timing/Power Optimization Feature in M20K Blocks
2.14. Intel Agilex® 7 Supported Embedded Memory IPs
3.1. Consider the Memory Block Selection
3.2. Consider the Concurrent Read Behavior
3.3. Customize Read-During-Write Behavior
3.4. Consider Power-Up State and Memory Initialization
3.5. Reduce Power Consumption
3.6. Avoid Providing Non-Deterministic Input
3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously
3.8. Advanced Settings in Intel® Quartus® Prime Software for Memory
3.9. Consider the Memory Depth Setting
3.10. Consider Registering the Memory Output
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs
4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters
4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters
4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters
4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters
4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters
4.1.7. Changing Parameter Settings Manually
4.1.8. RAM and ROM Interface Signals
4.3.1. Release Information for FIFO Intel® FPGA IP
4.3.2. Configuration Methods
4.3.3. Specifications
4.3.4. FIFO Functional Timing Requirements
4.3.5. SCFIFO ALMOST_EMPTY Functional Timing
4.3.6. FIFO Output Status Flag and Latency
4.3.7. FIFO Metastability Protection and Related Options
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect
4.3.9. SCFIFO and DCFIFO Show-Ahead Mode
4.3.10. Different Input and Output Width
4.3.11. DCFIFO Timing Constraint Setting
4.3.12. Coding Example for Manual Instantiation
4.3.13. Design Example
4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing
4.3.15. Guidelines for Embedded Memory ECC Feature
4.3.16. FIFO Intel® FPGA IP Parameters
4.3.17. Reset Scheme
4.4.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP
4.4.2. Shift Register (RAM-based) Intel® FPGA IP Features
4.4.3. Shift Register (RAM-based) Intel® FPGA IP General Description
4.4.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings
4.4.5. Shift Register Ports and Parameters Setting
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2.2.1. Byte Enable Controls
Byte Enable [1:0] | Data Bits Written | |
---|---|---|
11 (default) | [9:5] | [4:0] |
10 | [9:5] | N/A |
01 | N/A | [4:0] |
00 | N/A | N/A |
Byte Enable [1:0] | Data Bits Written | |
---|---|---|
11 (default) | [19:10] | [9:0] |
10 | [19:10] | N/A |
01 | N/A | [9:0] |
00 | N/A | N/A |
Byte Enable [3:0] | Data Bits Written | |||
---|---|---|---|---|
1111 (default) | [39:30] | [29:20] | [19:10] | [9:0] |
1110 | [39:30] | [29:20] | [19:10] | N/A |
1101 | [39:30] | [29:20] | N/A | [9:0] |
1100 | [39:30] | [29:20] | N/A | N/A |
1011 | [39:30] | N/A | [19:10] | [9:0] |
1010 | [39:30] | N/A | [19:10] | N/A |
1001 | [39:30] | N/A | N/A | [9:0] |
1000 | [39:30] | N/A | N/A | N/A |
0111 | N/A | [29:20] | [19:10] | [9:0] |
0110 | N/A | [29:20] | [19:10] | N/A |
0101 | N/A | [29:20] | N/A | [9:0] |
0100 | N/A | [29:20] | N/A | N/A |
0011 | N/A | N/A | [19:10] | [9:0] |
0010 | N/A | N/A | [19:10] | N/A |
0001 | N/A | N/A | N/A | [9:0] |
0000 | N/A | N/A | N/A | N/A |