Intel Agilex® 7 Embedded Memory User Guide

ID 683241
Date 6/26/2023

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3.10. M20K Embedded Memory Block Input Clock Quality Requirement

A stable input clock to the selected memory block is important to ensure the success of your Intel Agilex® 7 Embedded Memory designs.
  • Intel recommends using the PLL-generated clocks to ensure a clean and glitch-free clock source to your embedded memory block.
  • It is recommended that the PLL-generated clock is not routed to any other combinational user logic that may introduce glitches.
  • For any clock switchover events, ensure it is a synchronous clock switchover to avoid introducing any glitches to the clock path.
  • If you need to use an external I/O pin or an external clock source, you need to ensure it is glitch-free to avoid any performance issues. Please use the clock gating features available in the Embedded Memory or Clock Control IP if necessary.

For more information on optimal clocking performance, please refer to Optimizing Clocking Schemes in the Intel Quartus Prime Pro Edition User Guide: Design Recommendations and Intel Agilex® 7 Clocking and PLL User Guide for clocking and PLL design guidelines.