Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 6/26/2023

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2.3.2. Early Timing Analysis After Design Synthesis (Beta)

Early Timing Analysis flow is a beta feature. The SDC-on-RTL component of the Early Timing Analysis relies on enabling the DNI flow, which supports the underlying technology to read the constraints early in the compilation flow and use them in the later stages of the Intel® Quartus® Prime compilation. For more information about the DNI flow, refer to DNI Flow (Beta).

Once you enable the DNI flow, the compilation dashboard updates, and you can now access the Timing Analyzer right after design synthesis, as shown in the following image:

Figure 37. Early Timing Analysis Stage

Early Timing Analysis flow is a combination of Synopsys* Design Constraint (SDC) on RTL and post-synthesis static timing analysis. However, you can run the flow even without RTL SDCs where you can view the synthesized timing netlist. For more information, refer to Synopsys* Design Constraint (SDC) on RTL and Post-Synthesis Static Timing Analysis (STA).

Figure 38. Early Timing Analysis Flow

Early Timing Analysis flow involves running Analysis & Elaboration and Synthesis stages and iterating on your design's static timing analysis results early in the Intel® Quartus® Prime software compilation flow without running the Fitter. For additional information about each of the compilation stages listed in the Early Timing Analysis Flow diagram, refer to the following topics: