2.1. Compilation Overview 2.2. Using the Compilation Dashboard 2.3. Design Netlist Infrastructure (Beta) 2.4. Design Synthesis 2.5. Design Place and Route 2.6. Incremental Optimization Flow 2.7. Fast Forward Compilation Flow 2.8. Full Compilation Flow 2.9. Exporting Compilation Results 2.10. Integrating Other EDA Tools 2.11. Synthesis Language Support 2.12. Compiler Optimization Techniques 2.13. Synthesis Settings Reference 2.14. Fitter Settings Reference 2.15. Design Compilation Revision History
2.9.1. Exporting a Version-Compatible Compilation Database 2.9.2. Importing a Version-Compatible Compilation Database 2.9.3. Creating a Design Partition 2.9.4. Exporting a Design Partition 2.9.5. Reusing a Design Partition 2.9.6. Viewing Quartus Database File Information 2.9.7. Clearing Compilation Results
3.1. Factors Affecting Compilation Results 3.2. Strategies to Reduce the Overall Compilation Time 3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time 3.4. Reducing Placement Time 3.5. Reducing Routing Time 3.6. Reducing Static Timing Analysis Time 3.7. Setting Process Priority 3.8. Reducing Compilation Time Revision History
2.7.2. Step 2: Review Retiming Results
Follow these steps to review the results of register retiming. Use the results to determine if additional performance improvements are necessary and possible by removing retiming limits.
- To open the Retiming Limit Details report, click the Report icon for the Retime stage in the Compilation Dashboard. The Retiming Limit Details lists the number of registers moved, their paths, and the limiting reason preventing further retiming.
Figure 81. Retiming Limit Details
- To further optimize, resolve any Limiting Reason in your design, and then rerun the Retime stage, as necessary.
Table 21. Retiming Limit Details Report Data Report Data Description Clock Transfer Lists each clock domain in your design. Click the domain to display data about each entry. Limiting Reason Specifies any design condition that prevent further register retiming improvement, such as any of the following conditions:
- Insufficient Registers—indicates insufficient quantity of registers at either end of the chain for retiming. Adding more registers can improve performance.
- Short Path/Long Path—indicates that the critical chain has dependent paths with conflicting characteristics. For example, one path improves performance with more registers, and another path has no place for additional hyper-registers.
- Path Limit—indicates that there are no further Hyper-Register locations available on the critical path, or the design reached a performance limit of the current place and route.
- Loops—indicates a feedback path in a circuit. When the critical chain includes a feedback loop, retiming cannot change the number of registers in the loop without changing functionality. The Compiler can retime around the loop without changing functionality. However, the Compiler cannot place additional registers in the loop.
Critical Chain Details Lists register timing path associated with the retiming limitations. Right-click any path to Locate Critical Chain in Technology Map Viewer.
- If register retiming achieves all performance goals for your design, proceed to Fitter (Finalize) and Timing Analysis stages of compilation.
- If your design requires further optimization, run Fast Forward Timing Closure Recommendations as Step 3: Run Fast Forward Compile describes.