Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 6/26/2023

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Document Table of Contents Congestion due to HDL Coding style

Sometimes, routing congestion may be a result of the HDL coding style used in your design. After identifying congested areas using the Chip Planner, review the HDL code for the blocks placed in those areas to determine whether you can reduce interconnect usage by code changes.