2.1. Compilation Overview 2.2. Using the Compilation Dashboard 2.3. Design Netlist Infrastructure (Beta) 2.4. Design Synthesis 2.5. Design Place and Route 2.6. Incremental Optimization Flow 2.7. Fast Forward Compilation Flow 2.8. Full Compilation Flow 2.9. Exporting Compilation Results 2.10. Integrating Other EDA Tools 2.11. Synthesis Language Support 2.12. Compiler Optimization Techniques 2.13. Synthesis Settings Reference 2.14. Fitter Settings Reference 2.15. Design Compilation Revision History
2.9.1. Exporting a Version-Compatible Compilation Database 2.9.2. Importing a Version-Compatible Compilation Database 2.9.3. Creating a Design Partition 2.9.4. Exporting a Design Partition 2.9.5. Reusing a Design Partition 2.9.6. Viewing Quartus Database File Information 2.9.7. Clearing Compilation Results
3.1. Factors Affecting Compilation Results 3.2. Strategies to Reduce the Overall Compilation Time 3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time 3.4. Reducing Placement Time 3.5. Reducing Routing Time 3.6. Reducing Static Timing Analysis Time 3.7. Setting Process Priority 3.8. Reducing Compilation Time Revision History
2.7.5. Step 5: Implement Fast Forward Recommendations
Implement the Fast Forward timing closure recommendations in your design RTL and rerun synthesis and the Retime stage to perform Hyper-Retiming and realize the predictive performance gains. The amount and type of changes that you implement depends on your performance goals. For example, if you can achieve the target fMAX with simple asynchronous clear removal or conversion, you can stop design optimization after making those changes. For more information, refer to Retiming Restrictions and Workarounds.
- Implement one or more Fast Forward recommendations in your design RTL, such as any of the following techniques:
- Remove limitations of control logic, such as long feedback loops and state machines.
- Restructure logic to use functionally equivalent feed-forward or pre-compute paths, rather than long combinatorial feedback paths.
- Reduce the delay of ‘Long Paths’ in the chain. Use standard timing closure techniques to reduce delay. Excessive combinational logic, sub-optimal placement, and routing congestion cause delay on paths.
- Insert more pipeline stages in ‘Long Paths’ in the chain. Long paths have the most delay between registers in the critical chain.
- Increase the delay (or add pipeline stages to ‘Short Paths’ in the chain).
- Explore performance and implement the RTL changes to your code until you reach the desired performance target.
- Implement your RTL changes and perform Hyper-Retiming by re-running the Retime stage on the Compilation Dashboard (which also reruns prerequisite synthesis and fitting stages).