18.104.22.168. Post-Synthesis Static Timing Analysis (STA)
Post-synthesis STA defaults to the "Average Value" interconnect (IC) delay model to control STA after synthesis. Using the STA_POST_SYN_DELAY_MODEL QSF, you can switch to the "Zero Value" IC delay model to exclude interconnect delays from the timing model.
Post-synthesis static timing analysis (STA) uses a timing netlist comprising core block delays with no routing or periphery delays. This provides you with an early view of your design's core timing. You can run timing analysis reports and some design rules.
Perform the following steps to run post-synthesis STA:
- Create an Intel® Quartus® Prime software project using your design RTL and associated SDC-on-RTL SDC file.
- In the DNI flow, run Analysis and Elaboration compilation stage on your design as follows:
quartus_syn --dni --analysis_and_elaboration <design>
- Perform Synthesis on your design as follows:
quartus_syn --dni -–synthesis <design>
You can also perform the above steps using the Intel® Quartus® Prime software GUI with DNI flow enabled, as shown in the following image:
After running post-synthesis STA on your design, you can use the Timing Analyzer conventionally. However, a fundamental difference in the netlist topography is that the post-synthesis STA timing netlist has no connectivity inside any periphery block.
For post-synthesis constraints, Intel recommends using an SDC-on-RTL file. In cases where this is not possible, post-synthesis STA introduces the SYN_SDC_FILE QSF variable, which you can use to add a conventional SDC file to the QSF during post-synthesis STA. This QSF is beneficial for blocks that do not have SDC-on-RTL constraints available. Since the post-synthesis STA netlist differs from the post-plan STA netlist, conventional SDCs written for the post-plan netlist might not function during post-synthesis STA. By creating a new category of SDC files, you can identify scripts you want to load during post-synthesis STA.