Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 6/21/2022

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Document Table of Contents Preserving Registers During Synthesis

Intel® Quartus® Prime synthesis minimizes gate count, merges redundant logic, and ensures efficient use of device resources. If you need to preserve specific registers through synthesis processing, you can specify any of the following entity-level assignments.

Assign the Preserve Registers in Synthesis or Preserve Fan-Out Free Register Node options to allow Fitter optimization of the preserved registers. Preserve Registers restricts Fitter optimization of the preserved registers. Specify synthesis preservation assignments by clicking Assignments > Assignment Editor, by modifying the .qsf file, or by specifying synthesis attributes in your RTL.

Table 4.  Synthesis Preserve Options
Assignment Description Allows Fitter Optimization? Assignment Syntax
Preserve Registers in Synthesis Prevents removal of registers during synthesis. This settings does not affect retiming or other optimizations in the Fitter. Yes
  • PRESERVE_REGISTER_SYN_ONLY ON|Off -to <entity> .qsf
  • preserve_syn_only or syn_preservesyn_only (synthesis attributes)
Preserve Fan-Out Free Register Node Prevents removal of assigned registers without fan-out during synthesis.

The PRESERVE_FANOUT_FREE_NODE assignment cannot preserve a fanout-free register that has no fanout inside the Verilog HDL or VHDL module in which you define it. To preserve these fanout-free registers, implement the noprune pragma in the source file:

(*noprune*)reg r;

If there are multiple instances of this module, with only some instances requiring preservation of the fanout-free register, set a dummy pragma on the register in the HDL and also set the PRESERVE_FANOUT_FREE_NODE assignment. This dummy pragma allows the register synthesis to implement the assignment. For example, set the following dummy pragma for a register r in Verilog HDL:

(*dummy*)reg r;
  • no_prune on (synthesis attribute)
Preserve Registers Prevents removal and sequential optimization of assigned registers during synthesis. Sequential netlist optimizations can eliminate redundant registers and registers with constant drivers. No
  • PRESERVE_REGISTER ON|Off -to <entity> .qsf
  • preserve, syn_preserve, or keep on (synthesis attributes)