Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

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ID 683236
Date 6/21/2022
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Design Compilation 3. Reducing Compilation Time 4. Intel® Quartus® Prime Pro Edition User Guide Design Compilation Archives A. Intel® Quartus® Prime Pro Edition User Guides
2. Design Compilation x
2.1. Compilation Overview 2.2. Using the Compilation Dashboard 2.3. Design Netlist Infrastructure (DNI) 2.4. Design Synthesis 2.5. Design Place and Route 2.6. Incremental Optimization Flow 2.7. Fast Forward Compilation Flow 2.8. Full Compilation Flow 2.9. Exporting Compilation Results 2.10. Integrating Other EDA Tools 2.11. Synthesis Language Support 2.12. Compiler Optimization Techniques 2.13. Synthesis Settings Reference 2.14. Fitter Settings Reference 2.15. Design Compilation Revision History
2.1. Compilation Overview x
2.1.1. Compilation Flows 2.1.2. Compilation Hierarchy 2.1.3. Compilation Monitoring
2.3. Design Netlist Infrastructure (DNI) x
2.3.1. Exploring the RTL Analyzer 2.3.2. Sweep Hints Viewer
2.3.1. Exploring the RTL Analyzer x
2.3.1.1. Instances Bundling and Auto-hiding Unconnected Pins
2.4. Design Synthesis x
2.4.1. Running Synthesis 2.4.2. Viewing Synthesis Reports
2.4.1. Running Synthesis x
2.4.1.1. Preserving Registers During Synthesis 2.4.1.2. Preserving Signals for Monitoring and Debugging
2.5. Design Place and Route x
2.5.1. Running the Fitter 2.5.2. Viewing Fitter Reports
2.5.1. Running the Fitter x
2.5.1.1. Fitter Commands 2.5.1.2. Disabling or Enabling Physical Synthesis Optimization
2.5.2. Viewing Fitter Reports x
2.5.2.1. Plan Stage Reports 2.5.2.2. Place Stage Reports 2.5.2.3. Route Stage Reports 2.5.2.4. Retime Stage Reports 2.5.2.5. Finalize Stage Reports
2.5.2.2. Place Stage Reports x
2.5.2.2.1. Global Signal Visualization Report
2.5.2.3. Route Stage Reports x
2.5.2.3.1. Global Router Congestion Hotspot Summary Report 2.5.2.3.2. Global Router Wire Utilization Map Report
2.6. Incremental Optimization Flow x
2.6.1. Concurrent Analysis During Synthesis or Fitting 2.6.2. Analyzing Compiler Snapshots 2.6.3. Validating Periphery (I/O) after the Plan Stage
2.6.2. Analyzing Compiler Snapshots x
2.6.2.1. Running Snapshot Viewer
2.6.2.1. Running Snapshot Viewer x
2.6.2.1.1. Analyzing Failing Paths with Snapshot Viewer 2.6.2.1.2. Analyzing Clocking with Snapshot Viewer 2.6.2.1.3. Analyzing High Fan-out Nets with Snapshot Viewer 2.6.2.1.4. Validating Timing Constraints with Snapshot Viewer 2.6.2.1.5. Analyzing Congestion with Snapshot Viewer
2.7. Fast Forward Compilation Flow x
2.7.1. Step 1: Run Register Retiming 2.7.2. Step 2: Review Retiming Results 2.7.3. Step 3: Run Fast Forward Compile 2.7.4. Step 4: Review Fast Forward Results 2.7.5. Step 5: Implement Fast Forward Recommendations 2.7.6. Retiming Restrictions and Workarounds
2.7.2. Step 2: Review Retiming Results x
2.7.2.1. Locate Critical Chains
2.7.3. Step 3: Run Fast Forward Compile x
2.7.3.1. Fast Forward Compile By Hierarchy 2.7.3.2. HyperFlex Settings
2.7.4. Step 4: Review Fast Forward Results x
2.7.4.1. Clock Fmax Summary Report 2.7.4.2. Fast Forward Details Report
2.8. Full Compilation Flow x
2.8.1. Full Compilation Flow with Temporary Optimization Mode
2.9. Exporting Compilation Results x
2.9.1. Exporting a Version-Compatible Compilation Database 2.9.2. Importing a Version-Compatible Compilation Database 2.9.3. Creating a Design Partition 2.9.4. Exporting a Design Partition 2.9.5. Reusing a Design Partition 2.9.6. Viewing Quartus Database File Information 2.9.7. Clearing Compilation Results
2.9.6. Viewing Quartus Database File Information x
2.9.6.1. QDB File Attribute Types
2.10. Integrating Other EDA Tools x
2.10.1. Generating a VQM Netlist for other EDA Tools
2.11. Synthesis Language Support x
2.11.1. Verilog and SystemVerilog Synthesis Support 2.11.2. VHDL Synthesis Support
2.11.1. Verilog and SystemVerilog Synthesis Support x
2.11.1.1. Verilog HDL Input Settings (Settings Dialog Box) 2.11.1.2. Design Libraries 2.11.1.3. Verilog HDL Configuration 2.11.1.4. Initial Constructs and Memory System Tasks 2.11.1.5. Verilog HDL Macros
2.11.1.3. Verilog HDL Configuration x
2.11.1.3.1. Hierarchical Design Configurations
2.11.2. VHDL Synthesis Support x
2.11.2.1. VHDL Input Settings (Settings Dialog Box) 2.11.2.2. VHDL Standard Libraries and Packages 2.11.2.3. VHDL wait Constructs 2.11.2.4. VHDL-2019 Conditional Analysis Tool Directives
2.12. Compiler Optimization Techniques x
2.12.1. Compiler Optimization Modes 2.12.2. Allow Register Retiming 2.12.3. Automatic Gated Clock Conversion 2.12.4. Enable Intermediate Fitter Snapshots 2.12.5. Fast Preserve Option 2.12.6. Fractal Synthesis Optimization
2.12.6. Fractal Synthesis Optimization x
2.12.6.1. Enabling or Disabling Fractal Synthesis
2.13. Synthesis Settings Reference x
2.13.1. Advanced Synthesis Settings
3. Reducing Compilation Time x
3.1. Factors Affecting Compilation Results 3.2. Strategies to Reduce the Overall Compilation Time 3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time 3.4. Reducing Placement Time 3.5. Reducing Routing Time 3.6. Reducing Static Timing Analysis Time 3.7. Setting Process Priority 3.8. Reducing Compilation Time Revision History
3.2. Strategies to Reduce the Overall Compilation Time x
3.2.1. Running the ECO Compilation Flow 3.2.2. Enabling Multi-Processor Compilation 3.2.3. Using Block-Based Compilation
3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time x
3.3.1. Settings to Reduce Synthesis Time and Synthesis Netlist Optimization Time 3.3.2. Use Appropriate Coding Style to Reduce Synthesis Time
3.4. Reducing Placement Time x
3.4.1. Placement Effort Multiplier Settings
3.5. Reducing Routing Time x
3.5.1. Identifying Routing Congestion with the Chip Planner
3.5.1. Identifying Routing Congestion with the Chip Planner x
3.5.1.1. Areas with Routing Congestion 3.5.1.2. Congestion due to HDL Coding style
1. Answers to Top FAQs
2. Design Compilation
3. Reducing Compilation Time
4. Intel® Quartus® Prime Pro Edition User Guide Design Compilation Archives
A. Intel® Quartus® Prime Pro Edition User Guides

2.4.1.1. Preserving Registers During Synthesis

Intel® Quartus® Prime synthesis minimizes gate count, merges redundant logic, and ensures efficient use of device resources. If you need to preserve specific registers through synthesis processing, you can specify any of the following entity-level assignments.

Assign the Preserve Registers in Synthesis or Preserve Fan-Out Free Register Node options to allow Fitter optimization of the preserved registers. Preserve Registers restricts Fitter optimization of the preserved registers. Specify synthesis preservation assignments by clicking Assignments > Assignment Editor, by modifying the .qsf file, or by specifying synthesis attributes in your RTL.

Table 4.  Synthesis Preserve Options
Assignment Description Allows Fitter Optimization? Assignment Syntax
Preserve Registers in Synthesis Prevents removal of registers during synthesis. This settings does not affect retiming or other optimizations in the Fitter. Yes
  • PRESERVE_REGISTER_SYN_ONLY ON|Off -to <entity> .qsf
  • preserve_syn_only or syn_preservesyn_only (synthesis attributes)
Preserve Fan-Out Free Register Node Prevents removal of assigned registers without fan-out during synthesis.

The PRESERVE_FANOUT_FREE_NODE assignment cannot preserve a fanout-free register that has no fanout inside the Verilog HDL or VHDL module in which you define it. To preserve these fanout-free registers, implement the noprune pragma in the source file: 

(*noprune*)reg r;

If there are multiple instances of this module, with only some instances requiring preservation of the fanout-free register, set a dummy pragma on the register in the HDL and also set the PRESERVE_FANOUT_FREE_NODE assignment. This dummy pragma allows the register synthesis to implement the assignment. For example, set the following dummy pragma for a register r in Verilog HDL: 

(*dummy*)reg r;
 Yes
  • PRESERVE_REGISTER_FANOUT_FREE_NODE ON|Off -to <entity> .qsf
  • no_prune on (synthesis attribute)
Preserve Registers Prevents removal and sequential optimization of assigned registers during synthesis. Sequential netlist optimizations can eliminate redundant registers and registers with constant drivers. No
  • PRESERVE_REGISTER ON|Off -to <entity> .qsf
  • preserve, syn_preserve, or keep on (synthesis attributes)
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