Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 6/21/2022
Public

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2.12.3. Automatic Gated Clock Conversion

Clock gating saves power in ASIC designs by adding more logic to a circuit to prune the clock tree. Pruning the clock tree disables portions of the circuitry so that the flip-flops are not required to switch states. When using an Intel® Quartus® Prime FPGA to prototype ASIC designs, you must convert clock gates to clock enables in your design.
Gated Clock Conversion Example
ASIC Gated Clock Example FPGA Clock Enable Example
module infer_enable (clk, reset, d, en, q);

input d, en, clk, reset;
output q;

wire gated_clk;
reg q;

assign gated_clk = clk & en;
always@(posedge gated_clk or reset)
 begin
               if (!reset) 
                      q <= 1’b0;
              else 
                      q <= d ;
              end 
endmodule
module infer_enable (clk, reset, d, en, q);

input d, en, clk, reset;
output q;

reg q;

always@(posedge clk or reset)
 begin
               if (!reset) 
                     q <= 1’b0;
              else if (en)
                     q <= d;
              else 
                      q <= q ;
              end 
endmodule

Rather than manually converting gated clocks in your RTL, you can specify the Auto Gated Clock Conversion setting to automatically convert gated base clocks in the design to clock enables. You can apply this setting globally to all gated base clocks in the design, or to one or more specific clock signals.

Table 25.  Gated Clock Conversion Settings

Setting Scope

Description

Global Enable the Auto Gated Clock Conversion option at Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis). Alternatively, add the global assignment to the project .qsf:
set_global_assignment –name SYNTH_GATED_CLOCK_CONVERSION on
Instance-specific Specify the Auto Gated Clock Conversion for one or more instances in the Assignment Editor (Assignments > Assignment Editor). Alternatively, add the instance assignment to the project .qsf:
set_instance_assignment –name SYNTH_GATED_CLOCK_CONVERSION on –to clk_in
Following design synthesis, view the results of gated clock conversion in the Gated Clock Conversion Details report. The report lists all converted and unconverted gated clocks with their base clocks. For unconverted gated clocks, the report specifies the reason the clock is not converted.
Note: Automatic gated clock conversion supports explicit RAMs (such as WYSIWYG RAMs and Intel FPGA memory IP), but does not support inferred RAMs.
Figure 71.  Gated Clock Conversion Details Report