2.12.3. Automatic Gated Clock Conversion
|ASIC Gated Clock Example
|FPGA Clock Enable Example
Rather than manually converting gated clocks in your RTL, you can specify the Auto Gated Clock Conversion setting to automatically convert gated base clocks in the design to clock enables. You can apply this setting globally to all gated base clocks in the design, or to one or more specific clock signals.
|Enable the Auto Gated Clock Conversion option at Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis). Alternatively, add the global assignment to the project .qsf:
|Specify the Auto Gated Clock Conversion for one or more instances in the Assignment Editor (Assignments > Assignment Editor). Alternatively, add the instance assignment to the project .qsf: