Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 6/21/2022
Public

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2.5.2.1. Plan Stage Reports

The Plan stage reports describe the I/O, interface, and control signals discovered during the periphery planning stage of the Fitter.
Figure 17. Plan Stage Reports ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs)

For Intel® Arria® 10 and Intel® Cyclone® 10 GX designs, the Plan stage includes the Global & Other Fast Signals Summary report that allows you to verify which clocks the Compiler promotes to global clocks. Clock planning occurs after the Plan stage for Intel® Stratix® 10 and Intel® Agilex™ designs.