Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 6/21/2022
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2.12.1. Compiler Optimization Modes

You can enable one of the following optimization modes to focus the Compiler's optimization effort. The default setting is a Balanced strategy between optimization and compile time, or optimize specifically for Performance, Area, Routability, Power, or Compile Time. The settings affect synthesis and fitting results.
Table 24.  Optimization Modes (Compiler Settings Page)

Optimization Mode

Description

Implications

Balanced

(normal flow)

The Compiler optimizes synthesis for balanced implementation that respects timing constraints.

The default setting that produces a balance between optimization effort and compile time.

High performance effort

The Compiler increases the timing optimization effort during placement and routing, and enables timing-related Physical Synthesis optimizations (per register optimization settings).

Each additional optimization increases compilation time.
High performance with maximum placement effort Enables the same Compiler optimizations as High performance effort, with additional placement optimization effort. Each additional optimization increases compilation time.
High performance with aggressive power effort Enables the same Compiler optimizations as High performance effort, while performing additional optimizations to reduce dynamic-power. Each additional optimization increases compilation time.
Superior performance Enables the same Compiler optimizations as High performance effort, and adds more optimizations during Analysis & Synthesis to maximize design performance with a potential increase to logic area. If design utilization is very high, this mode can cause difficulty in fitting, which can also negatively affect overall optimization quality.
Superior performance with maximum placement effort Enables the same Compiler optimizations as Superior performance, with additional placement optimization effort. Each additional optimization increases compilation time.
Aggressive Area (reduces performance)

The Compiler makes aggressive effort to reduce the device area required to implement the design at the potential expense of design performance.

This mode reduces performance.
High placement routability effort The Compiler makes high effort to route the design at the potential expense of design area, performance, and compilation time. The Compiler spends additional time reducing routing utilization, which can improve routability and also saves dynamic power. Each additional optimization increases compilation time.
High packing routability effort The Compiler makes high effort to route the design at the potential expense of design area, performance, and compilation time. The Compiler spends additional time packing registers, which can improve routability and also saves dynamic power. Each additional optimization increases compilation time.
Optimize netlist for routability The Compiler implements netlist modifications to increase routability at the possible expense of performance. Each additional optimization increases compilation time. This mode can reduce performance.

Aggressive power

(reduces performance)

Makes aggressive effort to optimize synthesis for low power. The Compiler further reduces the routing usage of signals with the highest specified or estimated toggle rates, saving additional dynamic power but potentially affecting performance.

This mode reduces performance.

Aggressive Compile Time (reduces performance)

Especially useful during early design iterations, this mode reduces the compilation run time by 30% (on average) at the expense of design fMAX of 15% (on average). Run time reduction occurs through reduced effort and fewer performance optimizations. This mode also disables some detailed reporting functions.

This mode produces the fastest full-flow timing estimation with an approximate correlation to the high-effort modes.

  • This mode reduces performance.
  • Reduced effort levels can cause no-fits, especially on highly congested designs. Mitigate this potential by either partitioning and constraining the placement of congested parts of design, or by using a high effort or routability mode
  • This mode may not identify the same critical paths as a full-effort compile (similar to Compiler seed-effects).
  • This mode disables some detailed reporting functions and enables .qsf settings that cannot be overridden by other .qsf settings.
Fast Functional Test (hold-timing optimization only)

This mode produces a .sof bitstream file that you can use for on-board functional testing with minimal compile time. This mode further reduces compile time beyond Aggressive Compile Time mode by limiting timing optimizations to only those for hold requirements.

  • Reduced effort levels can cause no-fits, especially on highly congested designs. Mitigate this potential by either partitioning and constraining the placement of congested parts of design, or by using a high effort or routability mode. Refer to the Creating a Partition topic in this document and the Intel Quartus Prime Pro Edition User Guide: Design Constraints
  • This mode can require clock speeds outside the lock range of the PLL Intel FPGA IP. Mitigate this effect by using the adjust_pll ECO command to update the PLL IP after fitting.
  • This mode disables some detailed reporting functions and enables .qsf settings that cannot be overridden by other .qsf settings.
Note: If you enable extended optimization modes for Design Space Explorer II by use of .qsf assignments, and then subsequently open the Compiler Settings tab for that project revision, the Compiler Settings tab indicates that the extended optimization mode reverts to one of the Compiler Settings tab Optimization Modes.