External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 10/04/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.1. Simulation Options

The following simulation options are available with the example testbench to improve simulation speed:
  • Skip calibration—Loads memory configuration settings and enters user mode, providing the fastest simulation time.

Both simulation options represent accurate controller efficiency and do not take into account board skew. This may cause a discrepancy in the simulated interface latency numbers. For more information regarding simulation assumptions and differences between RTL simulation and post-fit implementation, refer to the Simulation Versus Hardware Implementation chapter in the Intel® Agilex™ EMIF IP Design Example User Guide.

Table 57.  Typical Simulation Times Using Intel® Agilex™ EMIF IP

Calibration Mode/Run Time (1)

Estimated Simulation Time

Small Interface (×8 Single Rank)

Large Interface (×72 Quad Rank)


  • Skip calibration
  • Preloads calculated settings

15 minutes

40 minutes

Note to Table:

  1. Uses one loop of driver test. One loop of driver is approximately 600 read or write requests, with burst length up to 64.
  2. Simulation times shown in this table are approximate measurements made using Synopsys VCS. Simulation times can vary considerably, depending on the IP configuration, the simulator used, and the computer or server used.