External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 10/04/2021

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8.1.1. Timing Analysis

Timing analysis of Intel® Agilex™ EMIF IP is somewhat simpler than that of earlier device families, because Intel® Agilex™ devices have more hardened blocks and fewer soft logic registers to be analyzed, because most are user logic registers.

Your Intel® Agilex™ EMIF IP includes a Synopsys Design Constraints File (.sdc) which contains timing constraints specific to your IP. The .sdc file also contains Tool Command Language (.tcl) scripts which perform various timing analyses specific to memory interfaces.