External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 10/04/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

11.10.1. Enabling the On-Chip Debug Port

To export the cal_debug port, set the Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port parameter to Export, when parameterizing the emif_cal IP.
Figure 188. Enabling the On-Chip Debug Port
You may then create your own logic to perform the desired read/write commands on the cal_debug Avalon® memory-mapped interface.
Figure 189. Connecting Your Own Logic