Intel® MAX® 10 JTAG Boundary-Scan Testing User Guide

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ID 683210
Date 11/01/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 JTAG BST Overview 2. JTAG BST Architecture 3. BST Operation Control 4. I/O Voltage Support in the JTAG Chain 5. Enabling and Disabling JTAG BST Circuitry 6. Guidelines for JTAG BST 7. Boundary-Scan Description Language Support A. Document Revision History for the Intel® MAX® 10 JTAG Boundary-Scan Testing User Guide
2. JTAG BST Architecture x
2.1. JTAG Pins 2.2. JTAG Circuitry Functional Model 2.3. JTAG Boundary-Scan Register
2.3. JTAG Boundary-Scan Register x
2.3.1. Boundary-Scan Cells in Intel® MAX® 10 I/O Pin
3. BST Operation Control x
3.1. JTAG IDCODE 3.2. JTAG Secure Mode 3.3. JTAG Private Instruction 3.4. JTAG Instructions
1. Intel® MAX® 10 JTAG BST Overview
2. JTAG BST Architecture
3. BST Operation Control
4. I/O Voltage Support in the JTAG Chain
5. Enabling and Disabling JTAG BST Circuitry
6. Guidelines for JTAG BST
7. Boundary-Scan Description Language Support
A. Document Revision History for the Intel® MAX® 10 JTAG Boundary-Scan Testing User Guide

2.1. JTAG Pins

Table 1.  JTAG Pin Descriptions
Pin Function Description
TDI Serial input pin for:
  • Instructions
  • Test data
  • Programming data
  • TDI is sampled on the rising edge of TCK
  • TDI pins have internal weak pull-up resistors.
TDO Serial output pin for:
  • Instructions
  • Test data
  • Programming data
  • TDO is sampled on the falling edge of TCK
  • The pin is tri-stated if data is not being shifted out of the device.
TMS Input pin that provides the control signal to determine the transitions of the TAP controller state machine.
  • TMS is sampled on the rising edge of TCK
  • TMS pins have internal weak pull-up resistors.
TCK The clock input to the BST circuitry. —

All the JTAG pins are powered by the VCCIO of I/O bank 1B. In JTAG mode, the I/O pins support the LVTTL/LVCMOS 3.3-1.5V standards.

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