Intel® MAX® 10 JTAG Boundary-Scan Testing User Guide

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ID 683210
Date 11/01/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 JTAG BST Overview 2. JTAG BST Architecture 3. BST Operation Control 4. I/O Voltage Support in the JTAG Chain 5. Enabling and Disabling JTAG BST Circuitry 6. Guidelines for JTAG BST 7. Boundary-Scan Description Language Support A. Document Revision History for the Intel® MAX® 10 JTAG Boundary-Scan Testing User Guide
2. JTAG BST Architecture x
2.1. JTAG Pins 2.2. JTAG Circuitry Functional Model 2.3. JTAG Boundary-Scan Register
2.3. JTAG Boundary-Scan Register x
2.3.1. Boundary-Scan Cells in Intel® MAX® 10 I/O Pin
3. BST Operation Control x
3.1. JTAG IDCODE 3.2. JTAG Secure Mode 3.3. JTAG Private Instruction 3.4. JTAG Instructions
1. Intel® MAX® 10 JTAG BST Overview
2. JTAG BST Architecture
3. BST Operation Control
4. I/O Voltage Support in the JTAG Chain
5. Enabling and Disabling JTAG BST Circuitry
6. Guidelines for JTAG BST
7. Boundary-Scan Description Language Support
A. Document Revision History for the Intel® MAX® 10 JTAG Boundary-Scan Testing User Guide

2.2. JTAG Circuitry Functional Model

The JTAG BST circuitry requires the following registers:

  • Instruction register—determines which action to perform and which data register to access.
  • Bypass register (1-bit long data register)—provides a minimum-length serial path between the TDI and TDO pins.
  • Boundary-scan register—shift register composed of all the BSCs of the device.
Figure 1. JTAG Circuitry Functional Model
  • Test access port (TAP) controller—controls the JTAG BST.
  • TMS and TCK pins—operate the TAP controller.
  • TDI and TDO pins—provide the serial path for the data registers.
  • The TDI pin also provides data to the instruction register to generate the control logic for the data registers.
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