Intel® MAX® 10 JTAG Boundary-Scan Testing User Guide

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ID 683210
Date 11/01/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 JTAG BST Overview 2. JTAG BST Architecture 3. BST Operation Control 4. I/O Voltage Support in the JTAG Chain 5. Enabling and Disabling JTAG BST Circuitry 6. Guidelines for JTAG BST 7. Boundary-Scan Description Language Support A. Document Revision History for the Intel® MAX® 10 JTAG Boundary-Scan Testing User Guide
2. JTAG BST Architecture x
2.1. JTAG Pins 2.2. JTAG Circuitry Functional Model 2.3. JTAG Boundary-Scan Register
2.3. JTAG Boundary-Scan Register x
2.3.1. Boundary-Scan Cells in Intel® MAX® 10 I/O Pin
3. BST Operation Control x
3.1. JTAG IDCODE 3.2. JTAG Secure Mode 3.3. JTAG Private Instruction 3.4. JTAG Instructions
1. Intel® MAX® 10 JTAG BST Overview
2. JTAG BST Architecture
3. BST Operation Control
4. I/O Voltage Support in the JTAG Chain
5. Enabling and Disabling JTAG BST Circuitry
6. Guidelines for JTAG BST
7. Boundary-Scan Description Language Support
A. Document Revision History for the Intel® MAX® 10 JTAG Boundary-Scan Testing User Guide

5. Enabling and Disabling JTAG BST Circuitry

The JTAG BST circuitry in Intel® MAX® 10 devices is automatically enabled after the power-up.

To ensure that you do not inadvertently enable the JTAG BST circuitry when it is not required, disable the circuitry permanently with pin connections as listed in the following table.

Table 6.  Pin Connections to Permanently Disable the JTAG BST Circuitry in Intel® MAX® 10 Devices
JTAG Pins Connection to Disable
TMS VCCIO supply of Bank 1B
TCK GND
TDI VCCIO supply of Bank 1B
TDO Leave open

You must enable this circuitry only if you use the BST or in-system programming (ISP) features.

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