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1. Intel® MAX® 10 JTAG BST Overview
2. JTAG BST Architecture
3. BST Operation Control
4. I/O Voltage Support in the JTAG Chain
5. Enabling and Disabling JTAG BST Circuitry
6. Guidelines for JTAG BST
7. Boundary-Scan Description Language Support
A. Document Revision History for the Intel® MAX® 10 JTAG Boundary-Scan Testing User Guide
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5. Enabling and Disabling JTAG BST Circuitry
The JTAG BST circuitry in Intel® MAX® 10 devices is automatically enabled after the power-up.
To ensure that you do not inadvertently enable the JTAG BST circuitry when it is not required, disable the circuitry permanently with pin connections as listed in the following table.
JTAG Pins | Connection to Disable |
---|---|
TMS | VCCIO supply of Bank 1B |
TCK | GND |
TDI | VCCIO supply of Bank 1B |
TDO | Leave open |
You must enable this circuitry only if you use the BST or in-system programming (ISP) features.