126.96.36.199. Single-Byte Write Operation
Single-byte write operation or when the PAGE_SIZE parameter has a value of one does not require the shift_bytes signal. Ensure that the data byte is available on the datain[7..0] signal and the memory address is available on the addr[23..0] signal before setting the write and wren signals to one.
If wren signal has a value of zero, the write operation is not carried out and the busy signal remains deasserted. If the memory region is protected (you can set this in the EPCS/EPCQ/EPCQ-L/EPCQ-A status register), then the write operation does not proceed, and the busy signal is deasserted. The IP core then asserts the illegal_write signal for two clock cycles to indicate that the command has been canceled. The write, datain[7..0], and addr[23..0] signals are registered on the rising edge of the clkin signal.
After the IP core receives the write command, it asserts the busy signal to indicate that the write operation is in progress. The busy signal stays asserted while the EPCS/EPCQ/EPCQ-L/EPCQ-A device is writing the data byte into the flash memory.
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