ASMI Parallel Intel® FPGA IP Core User Guide

ID 683205
Date 7/02/2019
Document Table of Contents

1.4.11. Enable 4-byte Addressing Operation for an EPCQ256/EPCQ-L256 or Larger Devices

The en4b_addr input port allows you to access all memory address of an EPCQ256/EPCQ-L256 or larger devices. These input ports are available when you use an EPCQ256/EPCQ-L256 or larger devices.
Note: The 4-byte addressing operation is supported for EPCQ256/EPCQ-L256 or larger devices only, so you must enable 4-byte addressing when you use an EPCQ256/EPCQ-L256 or larger devices.

To enable 4-byte addressing mode, pull the write enable signal (wren) high, followed by the en4b_addr signal for at least one clock cycle. If the wren signal has a value of zero, the 4-byte addressing operation will not be carried out even though the en4b_addr signal is being pulled to high. After the IP core receives the 4-byte addressing command, the IP core asserts the busy signal to indicate the operation is in progress.

Figure 19. Execution of 4BYTEADDREN For Enabling 4-byte Addressing ModeThis figure shows an example of the latency when the ASMI Parallel Intel® FPGA IP core is performing the 4-byte addressing operation. This figure does not reflect the true processing time.
Note: When the busy signal is deasserted, allow two clock cycles before sending a new signal. This delay allows the circuit to reset itself before executing the next command.