ASMI Parallel Intel® FPGA IP Core User Guide

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ID 683205
Date 7/02/2019
Public
Document Table of Contents
Document Table of Contents x
1. ASMI Parallel Intel® FPGA IP Core User Guide
1. ASMI Parallel Intel® FPGA IP Core User Guide x
1.1. Device Family Support 1.2. Ports and Parameters 1.3. Installing and Licensing Intel® FPGA IP Cores 1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements 1.5. ASMI Parallel Intel® FPGA IP Core User Guide Archives 1.6. Document Revision History for ASMI Parallel Intel® FPGA IP Core User Guide
1.2. Ports and Parameters x
1.2.1. Parameters 1.2.2. Input Ports 1.2.3. Output Ports
1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements x
1.4.1. Read Memory Capacity ID from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.2. Read Silicon ID from the EPCS Device 1.4.3. Protect a Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.4. Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.7. Read Status Register of the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.8. Erase Memory in a Specified Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.9. Erase Memory in Bulk on the EPCS/EPCQ/EPCQ-L256/EPCQ-A Device 1.4.10. Erase Memory in a Specified Die on the EPCQ-L512 and EPCQ-L1024 Device 1.4.11. Enable 4-byte Addressing Operation for an EPCQ256/EPCQ-L256 or Larger Devices 1.4.12. 4-byte Addressing Exit Operation for an EPCQ256/EPCQ-L256 or Larger Devices
1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.5.1. EPCQ/EPCQ-L/EPCQ-A Devices Extended SPI Dual and Quad I/O Instruction 1.4.5.2. EPCQ/EPCQ-L/EPCQ-A Devices Read Dummy Clock Instruction
1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.6.1. Single-Byte Write Operation 1.4.6.2. Page-Write Operation
1. ASMI Parallel Intel® FPGA IP Core User Guide

1.4.5.1. EPCQ/EPCQ-L/EPCQ-A Devices Extended SPI Dual and Quad I/O Instruction

Other than the standard SPI protocol, EPCQ/EPCQ-L/EPCQ-A devices also support fast read commands with multiple I/O data transfer. For standard SPI instruction, DQ0 only sends data to the EPCQ/EPCQ-L/EPCQ-A while DQ1 receives data from the EPCQ/EPCQ-L/EPCQ-A device. With multiple I/O, the instruction operation codes are sent in DQ0 and the rest of data is transferred in multiple data lines; two data lines (DQ0, DQ1) for dual I/O and four data lines (DQ0, DQ1, DQ2, DQ3) for quad I/O.
To use the fast read operation with multiple I/O, the command is the same as fast read operation with the standard I/O. For the multiple-byte and single-byte operations, refer to Figure 1 and Figure 2. The differences are handled in ASMI Parallel Intel® FPGA IP core and you only need to use the operation as per usual.

For EPCS/EPCQ/EPCQ-L/EPCQ-A devices, the IP core generates the first data byte on the dataout[7..0] port after eight cycles and then it appears for the read command. The eight cycles are the dummy clock cycles designated in ASMI Parallel Intel® FPGA IP core in accordance to the default dummy clock value in the EPCS/EPCQ/EPCQ-L/EPCQ-A datasheet. The EPCS/EPCQ/EPCQ-L/EPCQ-A standard I/O and EPCQ/EPCQ-L/EPCQ-A dual I/O have default dummy clock value of 8, while EPCQ/EPCQ-L/EPCQ-A quad I/O has default dummy clock value of 10. So, when selecting EPCQ/EPCQ-L/EPCQ-A quad I/O fast read operation, the IP core generates the first byte of data on the dataout[7..0]port after ten cycles, and then it appears for the read command.

If the rden signal is asserted for the subsequence data, the data from the next address appears on the dataout[7..0] port at every eight clock cycles for standard I/O, every four clock cycles for dual I/O, and every two clock cycles for quad I/O. Monitor the data_valid signal to ensure that you sample the dataout[7..0] signal only when the data_valid signal is asserted.

When you enable multiple I/O in fast read operation, the fast read and write operations have their equivalents in multiple I/O. Instruction operation codes are sent in DQ0 and the rest of data will be transferred in multiple data lines. Other instructions such as sector erase, read status, and others still operates in standard I/O mode.

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