ASMI Parallel Intel® FPGA IP Core User Guide

ID 683205
Date 7/02/2019
Document Table of Contents

1.4.7. Read Status Register of the EPCS/EPCQ/EPCQ-L/EPCQ-A Device

Use the read_status signal to instruct the IP core to read the status register of the EPCS/EPCQ/EPCQ-L/EPCQ-A device.
Figure 15. Reading a Status RegisterThis figure shows an example of the latency when the ASMI Parallel Intel® FPGA IP core is executing the read status register command. The latency shown does not correctly reflect the true processing time. It shows the command only.
Note: When the busy signal is deasserted, allow two clock cycles before sending a new signal. This delay allows the circuit to reset itself before executing the next command.

The IP core registers the read_status signal on the rising edge of the clkin signal. After the IP core receives the read_status signal, it asserts the busy signal to indicate that the read command is in progress. To prevent the IP core from re-registering the command and executing it again, deassert the read_status signal before the busy signal is deasserted.

The IP core ensures that the 8-bit status register value is available on the status_out[7..0] signal before deasserting the busy signal. You can sample the status_out[7..0] signal as soon as the busy signal is deasserted.

You must decode the 8-bit status register value to find out which sectors are protected.

The status_out[7..0] signal holds the value of the status register from the last read status command. The contents of the status register may have changed (via a sector protect command, for example). Therefore, before sampling the status_out[7..0] signal, you must issue a new read status command.