ASMI Parallel Intel® FPGA IP Core User Guide

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ID 683205
Date 7/02/2019
Public
Document Table of Contents
Document Table of Contents x
1. ASMI Parallel Intel® FPGA IP Core User Guide
1. ASMI Parallel Intel® FPGA IP Core User Guide x
1.1. Device Family Support 1.2. Ports and Parameters 1.3. Installing and Licensing Intel® FPGA IP Cores 1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements 1.5. ASMI Parallel Intel® FPGA IP Core User Guide Archives 1.6. Document Revision History for ASMI Parallel Intel® FPGA IP Core User Guide
1.2. Ports and Parameters x
1.2.1. Parameters 1.2.2. Input Ports 1.2.3. Output Ports
1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements x
1.4.1. Read Memory Capacity ID from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.2. Read Silicon ID from the EPCS Device 1.4.3. Protect a Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.4. Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.7. Read Status Register of the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.8. Erase Memory in a Specified Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.9. Erase Memory in Bulk on the EPCS/EPCQ/EPCQ-L256/EPCQ-A Device 1.4.10. Erase Memory in a Specified Die on the EPCQ-L512 and EPCQ-L1024 Device 1.4.11. Enable 4-byte Addressing Operation for an EPCQ256/EPCQ-L256 or Larger Devices 1.4.12. 4-byte Addressing Exit Operation for an EPCQ256/EPCQ-L256 or Larger Devices
1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.5.1. EPCQ/EPCQ-L/EPCQ-A Devices Extended SPI Dual and Quad I/O Instruction 1.4.5.2. EPCQ/EPCQ-L/EPCQ-A Devices Read Dummy Clock Instruction
1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.6.1. Single-Byte Write Operation 1.4.6.2. Page-Write Operation
1. ASMI Parallel Intel® FPGA IP Core User Guide

1.4.4. Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device

Use the read signal to instruct the IP core to read data from the EPCS/EPCQ/EPCQ-L/EPCQ-A device. The ASMI Parallel Intel® FPGA IP core supports two types of read data operation: multiple-byte and single-byte read.
Figure 7. Reading Multiple-ByteThis figure shows an example of the latency when the ASMI Parallel Intel® FPGA IP core is executing multiple-byte read command. The latency shown does not correctly indicate the true processing time. It shows the command only.
Note: When the busy signal is deasserted, allow two clock cycles before sending a new signal. This delay allows the circuit to reset itself before executing the next command.


Figure 8. Reading Single-ByteThis figure shows an example of single-byte read command. The latency shown does not correctly indicate the true processing time. It shows the command only.
Note: When the busy signal is deasserted, allow two clock cycles before sending a new signal. This delay allows the circuit to reset itself before executing the next command.


The IP core registers the read signal on the rising edge of the clkin signal. After the IP core receives the read command, it asserts the busy signal to indicate that the read command is in progress.

Ensure that the read address appears on the addr[23..0] signal before asserting the read signal. The rden signal must also be asserted to enable the read operation.

The first data byte then appears on the dataout[7..0] signal. The IP core then asserts the data_valid signal for one clock cycle, which indicates that the dataout[7..0]signal contains a new valid data.

If you enable the read_address[23..0] port in the IP parameter editor, the port reflects the memory address for each data byte that appears on dataout[7..0] signal.

If you want to continue reading sequential data from the EPCS/EPCQ/EPCQ-L/EPCQ-A device, the rden signal must remain asserted. This condition allows you to read every memory address from the EPCS/EPCQ/EPCQ-L/EPCQ-A device with a single read command.

For every eight clkin signal clock cycles, a new data byte from the next address appears on the dataout[7..0] signal with its corresponding memory address on the read_address[23..0] signal. The data_valid signal is asserted for one clock cycle after the new data byte is out on the dataout[7..0] signal. Use the data_valid signal as an indication to capture the new data byte.

After the second-to-last byte of data to be read appears on the dataout[7..0] signal, and the data_valid signal is asserted, deassert the rden signal to indicate the end of the read command. A new byte from the next address then appears on the dataout[7..0] signal, and the data_valid signal is reasserted before the IP core stops processing. Only then does the IP core deassert the busy signal.

For a single-byte read, simply assert the rden signal for one clock cycle in conjunction with the read signal, or deassert the rden signal any time before the first data appears on the dataout[7..0] signal, and the data_valid signal asserts for the first time.

Monitor the data_valid signal and sample the dataout[7..0] signal only when the data_valid signal has a value of one.

After read operation, the dataout[7..0] signal holds the value of the last byte read until you issue a new read command or reset the device.

Note: The read, rden, and addr[7..0] signals must adhere to setup and hold time requirements for the clkin signal. These signals must remain stable at the rising edge of the clkin signal.
Note: For EPCQ256/EPCQ_L256 or larger devices, the width of the addr and read_address signals is 32 bit.
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