Intel® Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 9/08/2023
Document Table of Contents I/O PLL Clock Gate

You can dynamically gate each output counter of the Intel® Stratix® 10 I/O PLL. This provides a useful alternative to the root clock gate because the root clock gate can gate only 1 of the 9 output counters.

However, the I/O PLL clock gate is not cycle-specific. When you use the I/O PLL clock gate, expect a delay of several clock cycles between the assertion or deassertion of the clock gate and the corresponding change to the clock signal. The number of delay cycles is non-deterministic because the enable signal must be synchronized into the clock domain of the output clock, ensuring a glitch-free gate.

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