Intel® Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 9/08/2023
Document Table of Contents Clock Sector

Each clock sector has dedicated sector clock (SCLK) and row clock network resources that can be accessed by the programmable clock network. Each clock sector is also surrounded by programmable clock network resources. On each side, there is a channel that contains 32 independent bidirectional clock wires. At each corner, there is a set of programmable clock switch multiplexers which can route between these clocks wires.

A signal on a vertical clock wire can enter the sector to its left or right via clock tap multiplexers. The clock tap multiplexer drives a sector clock, which distributes the signal to each row in the clock sector. In each row, there are six row clock resources which connect to all core functional blocks, PLLs, and I/O interfaces in the sector, and to adjacent transceivers.

Figure 3. Dedicated Clock Resources Within a Clock Sector
Note: Although a clock network can be as small as one sector, the clock architecture enables up to 32 global clocks per sector. However, the number of global clocks available can be lower if a clock region spans large portions of the chip. Intel® Quartus® Prime software automatically sizes and positions each global clock region optimally based on available hardware resources.

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