Intel® Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 9/08/2023
Public
Document Table of Contents

4.3.4.4. Design Example 4: Dynamic Phase Shift Using IOPLL Reconfig IP Core

This design example uses a 1SG280LU3F50E2VGS1 device to demonstrate the implementation of the I/O PLL dynamic phase shift reconfiguration using the IOPLL Reconfig IP core. This design example consists of the IOPLL IP core, IOPLL Reconfig IP core, and In-System Sources & Probes IP core.

The I/O PLL synthesizes two output clocks of 200 MHz with 0 ps phase shift on counter C0 output and counter C1 output at medium bandwidth. The input reference clock is 50 MHz.

The IOPLL Reconfig IP core connect to a state machine to perform the I/O PLL dynamic phase shift operation. A high pulse on the reset_SM input through the In-System Sources & Probes IP core triggers the I/O PLL dynamic phase shift operation. After the I/O PLL dynamic phase shift operation is complete, counter C1 is phase shifted 89 ps for one positive phase shift step.

To run the test with this design example, perform these steps:

  1. Download and restore the iopll-reconfig-dynamic-phase-shift.qar file.
  2. Change the device and pin assignments of the design example to match your hardware.
  3. Recompile the design example. Ensure that the design example does not contain any timing violation after recompilation.
  4. Open the AN.stp file and program the device with top.sof.
  5. Assert a high pulse on the reset_SM signal to start the I/O PLL dynamic phase shift reconfiguration operation.
Figure 29. Waveform Example for Dynamic Phase Shift Using IOPLL Reconfig IP Core Design Example