AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

ID 683183
Date 12/18/2017
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Transmitter Data Link Layer

This test area covers the test cases for code group synchronization (CGS) and initial lane alignment sequence (ILAS).

On link start up, the receiver issues a synchronization request and the transmitter transmits /K/ (K28.5) characters. The Signal Tap Logic Analyzer tool monitors the transmitter data link layer operation.