AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

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ID 683183
Date 12/18/2017
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Document Table of Contents
Document Table of Contents x
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report x
Hardware Requirements Hardware Setup AD9371 EVM Software Setup Hardware Checkout Methodology for JESD204B Transmitter JESD204B IP Core and DAC Configurations Hardware Checkout Methodology for JESD204B Receiver JESD204B IP Core and Main ADC Configurations Deterministic Latency (Subclass 1) Test Results Test Result Comments Document Revision History for AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Hardware Checkout Methodology for JESD204B Transmitter x
Transmitter Data Link Layer Transmitter Transport Layer Scrambling
Transmitter Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization
Hardware Checkout Methodology for JESD204B Receiver x
Receiver Data Link Layer Receiver Transport Layer Descrambling
Receiver Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

Descrambling

The test setup is similar to test case RX_TL.1 except that the descrambler at the JESD204B receiver IP core and the scrambler at the ADC JESD transmitter core are enabled.

The Signal Tap II Logic Analyzer tool monitors the operation of the receiver transport layer.

Table 9.  Descrambler Test Cases
Test Case Objective Description Passing Criteria

RX_SCR.1

Check the functionality of the descrambler using sine wave test pattern.

Enable scrambler at the ADC and descrambler at the JESD204B receiver IP Core.

The signals that are tapped in this test case are similar to test case TL.1
  • The jesd204_rx_data_valid signal is asserted.
  • The jesd204_rx_int signals are deasserted.
  • Monotone sine wave with frequency same as that of transmitted monotone is observed in Signal Tap II when DAC analog output is looped back to ADC analog input.
Level Two Title