AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
ID
683183
Date
12/18/2017
Public
Hardware Requirements
Hardware Setup
AD9371 EVM Software Setup
Hardware Checkout Methodology for JESD204B Transmitter
JESD204B IP Core and DAC Configurations
Hardware Checkout Methodology for JESD204B Receiver
JESD204B IP Core and Main ADC Configurations
Deterministic Latency (Subclass 1)
Test Results
Test Result Comments
Document Revision History for AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Scrambling
The test setup is similar to test case TX_TL.1 except that the scrambler at the JESD204B transmitter IP core and the descrambler at the DAC JESD core are enabled.
The Signal Tap II Logic Analyzer tool monitors the operation of the transmitter transport layer.
Test Case | Objective | Description | Passing Criteria |
---|---|---|---|
TX_SCR.1 |
Verify the data transfer from digital to analog domain. |
Enable descrambler at the DAC JESD core and scrambler at the JESD204B transmitter IP core. Enable sine wave generator in the FPGA and observe the DAC analog channel output on the oscilloscope. |
A monotone sine wave is observed on the oscilloscope. |