The test setup is similar to test case TX_TL.1 except that the scrambler at the JESD204B transmitter IP core and the descrambler at the DAC JESD core are enabled.
The Signal Tap II Logic Analyzer tool monitors the operation of the transmitter transport layer.
Verify the data transfer from digital to analog domain.
Enable descrambler at the DAC JESD core and scrambler at the JESD204B transmitter IP core.
Enable sine wave generator in the FPGA and observe the DAC analog channel output on the oscilloscope.
A monotone sine wave is observed on the oscilloscope.