AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

ID 683183
Date 12/18/2017
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JESD204B IP Core and Main ADC Configurations

The JESD204B IP Core parameters (L, M, and F) in this hardware checkout are natively supported by the AD9371 device. The transceiver data rate, sampling clock frequency, and other JESD204B parameters comply with the AD9371 operating conditions.

The hardware checkout testing implements the JESD204B IP Core with the following parameter configuration.

Table 10.  Main ADC Parameter Configuration

Configuration

Mode

Mode

Mode

Mode

Mode

Mode

LMF

124

222

421 10

148

244

442

HD

0

0

1

0

0

0

S

1

1

1

1

1

1

N

16

16

16

16

16

16

N’

16

16

16

16

16

16

CS

0

0

0

0

0

0

CF

0

0

0

0

0

0

Subclass

1

1

1

1

1

1

Lane Rate (Gbps)

6.144

3.072

1.536 10

6.144

6.144

3.072

ADC IQ rate(MSPS)

153.6

153.6

153.6

76.8

153.6

153.6

AD9371 Device Clock (MHz)

153.6

153.6

153.6

153.6

153.6

153.6

FPGA Device Clock (MHz) 11

153.6

153.6

153.6

153.6

153.6

153.6

FPGA Management Clock (MHz)

100

100

100

100

100

100

FPGA Frame Clock (MHz) 12

153.6

153.6

38.4

76.8

153.6

76.8

FPGA Link Clock (MHz) 12

153.6

76.8

38.4

153.6

153.6

76.8

ADC RF local oscillator frequency (GHz)

1.0

1.0

1.0

1.0

1.0

1.0

Character Replacement

Enabled

Enabled

Enabled

Enabled

Enabled

Enabled

PCS Option

Hard PCS

Hard PCS

Hard PCS

Hard PCS

Hard PCS

Hard PCS

Data Pattern

Sine 13

Single pulse 14

Sinc 14

Sine 13

Single pulse 14

Sinc 14

Sine 13

Single pulse 14

Sinc 14

Sine 13

Single pulse 14

Sinc 14

Sine 13

Single pulse 14

Sinc 14

Sine 13

Single pulse 14

Sinc 14

10 JESD204B Mode with LMF=421 cannot be interoperated with Intel® Arria® 10 devices because the lane rate supported by Intel® Arria® 10 devices are 2 Gbps-15 Gbps. Because of limited ADC IQ rate, the mode LMF=421 can only reach 1.536 Gbps in the converter side.
11 The device clock is used to clock the transceiver.
12 The frame clock and link clock are derived from the device clock using an internal PLL.
13 Sine wave pattern is used in RX_TL.1 and RX_SCR.1 test cases to verify that pattern generated into ADC analog channel is converted into same pattern in the FPGA transport layer and at same frequency.
14 Single pulse and sinc pattern are used in deterministic latency measurement test cases DL.3 and DL.4 only.