AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

ID 683183
Date 12/18/2017
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Initial Frame and Lane Synchronization

Table 2.  Initial Frame and Lane Synchronization Test Cases
Test Case Objective Description Passing Criteria

TX_ILA.1

Check that the /R/ and /A/ characters are transmitted at the beginning and end of each multiframe.

Verify that four multiframes are transmitted in ILAS phase and receiver detects the initial lane alignment sequence correctly.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

  • jesd204_tx_pcs_data[(L*32)-1:0]
  • jesd204_tx_pcs_kchar_data[(L*4)-1:0] 2

The following signals in <ip_variant_name>.v are tapped:

  • sync_n
  • jesd204_tx_int

The txlink_clk is used as the sampling clock for the Signal Tap.

Each lane is represented by 32-bit data bus in jesd204_tx_pcs_data. The 32-bit data bus for is divided into 4 octets.

Check the following status in the AD9371 registers:

  • Frame Synchronization
  • The /R/ character or K28.0 (0x1C) is transmitted at the jesd204_tx_pcs_data bus to mark the beginning of multiframe.
  • The /A/ character or K28.3 (0x7C) is transmitted at the jesd204_tx_pcs_data bus to mark the end of each multiframe.
  • The sync_n and jesd204_tx_int signals are deasserted.
  • The jesd204_tx_pcs_kchar_data signal is asserted whenever control characters like /K/, /R/, /Q/, or /A/ are transmitted.
  • On reading status using ‘MYKONOS_readDeframerStatus’ API, No framing error bits should be set. bits[2:0] if set indicate framing errors.

TX_ILA.2

Check the JESD204B configuration parameters are transmitted in the second multiframe.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

  • jesd204_tx_pcs_data[(L*32)-1:0] 2

The following signal in <ip_variant_name>.v is tapped:

  • jesd204_tx_int

The txlink_clk is used as the sampling clock for the Signal Tap.

The Nios® console accesses the following JESD204B CSR registers:

  • ilas_data1
  • ilas_data2

The content of 14 configuration octets in second multiframe is stored in the above 32-bit registers.

Check the following status and error in the AD9371 register:

  • Good Checksum
  • Configuration Mismatch Error
  • The /R/ character is followed by /Q/ character or K28.4 (0x9C) in the jesd204_tx_pcs_data at the beginning of second multiframe.
  • The jesd204_tx_int is deasserted if there is no error.
  • The JESD204B parameters read from ilas_data1, ilas_data2 registers are the same as the parameters set in the JESD204B IP Core Platform Designer parameter editor.
  • On reading status using ‘MYKONOS_readDeframerStatus’ API, valid checksum bit should be set. bit[3] indicates valid checksum.
  • On reading status using ‘MYKONOS_jesd204bIlasCheck’ API, bit 15 which indicates ILAS configuration mismatch, should not be asserted.

TX_ILA.3

Check the constant pattern of transmitted user data after the end of 4th multiframe.

Verify that the receiver successfully enters user data phase.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

  • jesd204_tx_pcs_data[(L*32)-1:0] 2

The following signals in <ip_variant_name>.v are tapped:

  • jesd204_tx_int

The txlink_clk is used as the sampling clock for the Signal Tap.

The Nios console accesses the JESD204B CSR register - tx_err.

Check the following errors in the AD9371 register:

  • Lane FIFO pointer delta
  • When scrambler is turned off, the first user data is transmitted after the last /A/ character, which marks the end of the 4th multiframe transmitted. 3
  • Bits 2 and 3 of the JESD204B tx_err register are not set to “1”.
  • The “Lane FIFO Full” and “Lane FIFO Empty” in the AD9371 registers 0x30C and 0x30D should not be asserted.
  • The jesd204_tx_int is deasserted if there is no error.
2 L is the number of lanes.
3 When scrambler is turned on, your data pattern cannot be recognized after the 4th multiframe in ILAS phase.