Intel® MAX® 10 User Flash Memory User Guide

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ID 683180
Date 8/30/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 User Flash Memory Overview 2. Intel® MAX® 10 UFM Architecture and Features 3. Intel® MAX® 10 UFM Design Considerations 4. Intel® MAX® 10 UFM Implementation Guides 5. On-Chip Flash Intel® FPGA IP Core References 6. Intel® MAX® 10 User Flash Memory User Guide Archive 7. Document Revision History for the Intel® MAX® 10 User Flash Memory User Guide
2. Intel® MAX® 10 UFM Architecture and Features x
2.1. UFM and CFM Array Size 2.2. UFM Memory Organization Map 2.3. UFM Block Diagrams 2.4. UFM Operating Modes
3. Intel® MAX® 10 UFM Design Considerations x
3.1. Guideline: UFM Power Supply Requirement 3.2. Guideline: Program and Read UFM with JTAG 3.3. Guideline: UFM Content Initialization 3.4. Guideline: Erase Before Program
4. Intel® MAX® 10 UFM Implementation Guides x
4.1. On-Chip Flash Intel® FPGA IP Core 4.2. UFM Avalon-MM Operating Modes 4.3. Flash Initialization Files
4.2. UFM Avalon-MM Operating Modes x
4.2.1. UFM Read Status and Control Register 4.2.2. UFM Write Control Register 4.2.3. UFM Program (Write) Operation 4.2.4. UFM Sector Erase Operation 4.2.5. UFM Page Erase Operation 4.2.6. UFM Read Operation 4.2.7. UFM Burst Read Operation
4.2.7. UFM Burst Read Operation x
4.2.7.1. UFM Data Incrementing Burst Read 4.2.7.2. UFM Data Wrapping Burst Read
5. On-Chip Flash Intel® FPGA IP Core References x
5.1. On-Chip Flash Intel® FPGA IP Core Parameters 5.2. On-Chip Flash Intel® FPGA IP Core Signals 5.3. On-Chip Flash Intel® FPGA IP Core Registers
5.3. On-Chip Flash Intel® FPGA IP Core Registers x
5.3.1. Sector Address
1. Intel® MAX® 10 User Flash Memory Overview
2. Intel® MAX® 10 UFM Architecture and Features
3. Intel® MAX® 10 UFM Design Considerations
4. Intel® MAX® 10 UFM Implementation Guides
5. On-Chip Flash Intel® FPGA IP Core References
6. Intel® MAX® 10 User Flash Memory User Guide Archive
7. Document Revision History for the Intel® MAX® 10 User Flash Memory User Guide

5.2. On-Chip Flash Intel® FPGA IP Core Signals

The following table lists the signals for the On-Chip Flash Intel® FPGA IP core.
Table 9.  Avalon-MM Slave Input and Output Signals for Parallel and Serial Modes.
Signal Width Direction Description
Clock and Reset
clock 1 Input System clock signal that clocks the entire peripheral.
reset_n 1 Input System synchronous reset signal that resets the entire peripheral. The IP core asserts this signal asynchronously. This signal becomes synchronous in the IP core after the rising edge of the clock.
Control
avmm_csr_addr 1 Input Avalon-MM address bus that decodes registers.
avmm_csr_read 1 Input Avalon-MM read control signal. The IP core asserts this signal to indicate a read transfer. If present, the readdata signal is required.
avmm_csr_readdata 32 Output Avalon-MM read back data signal. The IP core asserts this signal during read cycles.
avmm_csr_write 1 Input Avalon-MM write control signal. The IP core asserts this signal to indicate a write transfer. If present, the writedata signal is required.
avmm_csr_writedata 32 Input Avalon-MM write data bus. The bus master asserts this bus during write cycles.
Data
avmm_data_addr User-defined Input Avalon-MM address bus that indicates the flash data address. The width of this address depends on your selection of device and configuration mode.
avmm_data_read 1 Input Avalon-MM read control signal. The IP core asserts this signal to indicate a read transfer. If present, the readdata signal is required.
avmm_data_readdata
  • Parallel mode: 32
  • Serial mode: 1
 Output Avalon-MM read back data signal. The IP core asserts this signal during read cycles.
avmm_data_write 1 Input Avalon-MM write control signal. The IP core asserts this signal to indicate a write transfer. If present, the writedata signal is required.
avmm_data_writedata
  • Parallel mode: 32
  • Serial mode: 1
 Input Avalon-MM write data bus. The bus master asserts this bus during write cycles.
avmm_data_waitrequest 1 Output The IP core asserts this bus to pause the master when the IP core is busy during read or write operations.
avmm_data_readdatavalid 1 Output The IP core asserts this signal when the readdata signal is valid during read cycles.
avmm_data_burstcount User-defined Input The bus master asserts this signal to initiate a burst read operation.
  • In write operations, the burst count is always fixed to 1 for parallel mode and 32 for serial mode.
  • In incrementing burst read mode, the supported read burst count range:
    Parallel mode 1-2(burstcount width-1)
    Serial mode 1-128*32
  • In wrapping burst read mode (parallel mode only), the supported read burst count is fixed to 2 and 4.
    10M04, and 10M08 1–2
    10M16, 10M25, 10M40 and 10M50 1–4
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