Intel® MAX® 10 User Flash Memory User Guide

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ID 683180
Date 8/30/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 User Flash Memory Overview 2. Intel® MAX® 10 UFM Architecture and Features 3. Intel® MAX® 10 UFM Design Considerations 4. Intel® MAX® 10 UFM Implementation Guides 5. On-Chip Flash Intel® FPGA IP Core References 6. Intel® MAX® 10 User Flash Memory User Guide Archive 7. Document Revision History for the Intel® MAX® 10 User Flash Memory User Guide
2. Intel® MAX® 10 UFM Architecture and Features x
2.1. UFM and CFM Array Size 2.2. UFM Memory Organization Map 2.3. UFM Block Diagrams 2.4. UFM Operating Modes
3. Intel® MAX® 10 UFM Design Considerations x
3.1. Guideline: UFM Power Supply Requirement 3.2. Guideline: Program and Read UFM with JTAG 3.3. Guideline: UFM Content Initialization 3.4. Guideline: Erase Before Program
4. Intel® MAX® 10 UFM Implementation Guides x
4.1. On-Chip Flash Intel® FPGA IP Core 4.2. UFM Avalon-MM Operating Modes 4.3. Flash Initialization Files
4.2. UFM Avalon-MM Operating Modes x
4.2.1. UFM Read Status and Control Register 4.2.2. UFM Write Control Register 4.2.3. UFM Program (Write) Operation 4.2.4. UFM Sector Erase Operation 4.2.5. UFM Page Erase Operation 4.2.6. UFM Read Operation 4.2.7. UFM Burst Read Operation
4.2.7. UFM Burst Read Operation x
4.2.7.1. UFM Data Incrementing Burst Read 4.2.7.2. UFM Data Wrapping Burst Read
5. On-Chip Flash Intel® FPGA IP Core References x
5.1. On-Chip Flash Intel® FPGA IP Core Parameters 5.2. On-Chip Flash Intel® FPGA IP Core Signals 5.3. On-Chip Flash Intel® FPGA IP Core Registers
5.3. On-Chip Flash Intel® FPGA IP Core Registers x
5.3.1. Sector Address
1. Intel® MAX® 10 User Flash Memory Overview
2. Intel® MAX® 10 UFM Architecture and Features
3. Intel® MAX® 10 UFM Design Considerations
4. Intel® MAX® 10 UFM Implementation Guides
5. On-Chip Flash Intel® FPGA IP Core References
6. Intel® MAX® 10 User Flash Memory User Guide Archive
7. Document Revision History for the Intel® MAX® 10 User Flash Memory User Guide

5.3. On-Chip Flash Intel® FPGA IP Core Registers

The following table lists the address mapping and registers for the On-Chip Flash Intel® FPGA IP core.
Table 10.  On-Chip Flash Intel® FPGA IP Core Control Address Mapping
Register Address Access Description
Status Register 0×00 Read only Stores the status and result of recent operations and sector protection mode.
Control Register 0×01 Read/Program Stores the following information:
  • Page erase address
  • Sector erase address
  • Sector write protection mode
Table 11.  On-Chip Flash Intel® FPGA IP Core Status Register
Bit Offset Field Default Value Description
1–0 busy 2'b00

2'b00 IDLE

2'b01 BUSY_ERASE

2'b10 BUSY_WRITE

2'b11 BUSY_READ
2 rs (read successful) 1'b0

1'b0 Read failed

1'b1 Read successful
3 ws (write successful) 1'b0

1'b0 Write failed

1'b1 Write successful
4 es (erase successful) 1'b0

1'b0 Erase failed

1'b1 Erase successful
5 sp (Sector ID 1 protection bit) — The IP core sets these bits based on the device, and configuration and access mode settings you specify during instantiation. These settings are fixed. If the IP core sets one of these bits, you cannot read or program on the specified sector.
6 sp (Sector ID 2 protection bit) —
7 sp (Sector ID 3 protection bit) —
8 sp (Sector ID 4 protection bit) —
9 sp (Sector ID 5 protection bit) —
31–10 dummy (padding) — All of these bits are set to 1.
Table 12.  On-Chip Flash Intel® FPGA IP Core Control Register
Bit Offset Field Default Value Description
19–0 pe (page erase address) All 1's

Sets the page erase address to initiate a page erase operation. The IP core only accepts the page erase address when it is in IDLE state. Otherwise, the page address will be ignored.

The legal value is any available address. The IP core erases the corresponding page of the given address.

22–20 se (sector erase address) 3'b111
Sets the sector erase address to initiate a sector erase operation. The IP core only accepts the sector erase address when it is in IDLE state. Otherwise, the page address will be ignored.
3'b001 Sector ID 1
3'b010 Sector ID 2
3'b011 Sector ID 3
3'b100 Sector ID 4
3'b101 Sector ID 5
Other values Illegal address
If the device you selected has only 3 sectors, the value mapped to sectors ID 4 and 5 will become illegal address.
Note: If you set both sector address and page address at the same time, the sector erase address gets the priority. The IP core accepts and executes the sector erase address and ignores the page erase address.

For more detailed description, refer to Sector Address.

23 wp (Sector ID 1 write protection) 1
The IP core uses these bits to protect the sector from write and erase operation. You must clear the corresponding sector write protection bit before your program or erase the sector.
1'b0 Disable write protected mode
1'b1 Enable write protected mode
24 wp (Sector ID 2 write protection) 1
25 wp (Sector ID 3 write protection) 1
26 wp (Sector ID 4 write protection) 1
27 wp (Sector ID 5 write protection) 1
31–28 dummy (padding) — All of these bits are set to 1.

Section Content
Sector Address

Level Two Title